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Chapter 5. Sequential Circuits: Flip-Flops and Counter By Taweesak Reungpeerakul. Contents. Introduction Latches Edge-Triggered Flip-Flops (ET-FFs) Operating Characteristics and Application Asynchronous Counter Synchronous Counter Cascaded Counters Counter Decoding

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### Chapter 5

Sequential Circuits: Flip-Flops and Counter

By Taweesak Reungpeerakul

241-208 CH7

Contents
• Introduction
• Latches
• Edge-Triggered Flip-Flops (ET-FFs)
• Operating Characteristics and Application
• Asynchronous Counter
• Synchronous Counter
• Counter Decoding
• Counter Applications
• Conclusions

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Contents
• Basic Shift Register Functions
• Serial In/Serial Out Shift Registers
• Serial In/Parallel Out Shift Registers
• Parallel In/Serial Out Shift Registers
• Parallel Out/Parallel Out Shift Registers
• Bidirectional Shift Registers
• Shift Register Counters
• Shift Register Applications
• Conclusions

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Introduction

Well, what u learned before is just one class of digital circuits.

In fact we can classify into two main classes :-

Output can depend on the

past and present inputs/outputs.

Output depends on the present input.

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Introduction (cont.)

Synchronous VS Asynchronous

• All state transitions are
• controlled by a common clock
• Changes in all variables occur
• concurrently
• State transitions occur independently
• of any clock
• Changes in all variables do not
• necessarily occur concurrently

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S

Q

Q

R

Latches
• A latch is a temporary storage device that has two stable states (bistable). It is a basic form of memory.
• The S-R (Set-Reset) latch is the most basic type. It can be constructed from NOR gates or NAND gates.

R

Q

Q

S

NOR Active-HIGH Latch NAND Active-LOW Latch

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R

R

Q

Q

S

S

Q

Q

S-R Latch

The active-HIGH S-R latch is in a stable (latched) condition when both inputs are LOW.

0

0

1

Latch initially RESET

Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (0). To SET the latch (Q = 1), a momentary HIGH signal is applied to the S input while the R remains LOW.

0

1

0

0

1

0

Latch initially SET

To RESET the latch (Q = 0), a momentary HIGH signal is applied to the R input while the S remains LOW.

0

1

0

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Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (1). To SET the latch (Q = 1), a momentary LOW signal is applied to the S input while the R remains HIGH.

S

R

S

To RESET the latch a momentary LOW is applied to the R input while S is HIGH.

Q

Q

R

S-R Latch (cont.)

The active-LOW S-R latch is in a stable (latched) condition when both inputs are HIGH.

1

1

0

Q

Latch initially RESET

1

0

1

1

0

1

Q

Latch initially SET

0

1

Never apply an active set and reset at the same time (invalid).

1

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Q

Latch with Enable

A gated latch is a variation on the basic latch.

The gated latch has an additional input, called enable (EN) that must be HIGH in order for the latch to respond to the S and R inputs.

S

Q

EN

Show the Q output with relation to the input signals. Assume Q starts LOW.

Example

R

Solution

Keep in mind that S and R are only active when EN is HIGH.

S

R

EN

Q

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Q

Q

D Latch

The D latch is an variation of the S-R latch but combines the S and R inputs into a single D input as shown:

D

Q

D

Q

EN

EN

A simple rule for the D latch is:

Q follows D when the Enable is active.

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Truth Table of D Latch

The truth table for the D latch summarizes its operation. If EN is LOW, then there is no change in the output and it is latched.

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Q

Notice that the Enable is not active during these times, so the output is latched.

Example

Q

D

EN

Determine the Q output for the D latch, given the inputs shown.

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Edge-Triggered Flip-Flops

Circuit type: Synchronous bistable device

Q:What is bistable ?

A: Remain in one of two stable states until it receives a pulse

(logic 1 signal) through one of its inputs, upon which it switches, or ‘flips’, over to the other state.

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Edge-Triggered Flip-Flops (cont.)
• ET-FF characteristics:
• 1-bit storage devices
• Why? 1) Since outputs can be set to store either ‘0’ or ‘1’, depending on the inputs
• 2) outputs retain their prescribed values (bistable prop.)
• FF have 2 complimentary outputs (Q, Q)
• Three main FF types: R-S, D-type, J-K
• Changes state either at the positive or negative edge of the clock pulse

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Edge-Triggered Flip-Flops (cont.)

The active edge can be positive or negative.

Dynamic input indicator

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Q

Edge-Triggered Flip-Flops (cont.)
• More versatile than other FFs.
• Has 2 inputs (J and K) and 2 outputs

Q

J

CLK

K

Positive ET-J-K FF

symbol

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Q

Edge-Triggered Flip-Flops (cont.)

Q

J

CLK

K

Positive ET-J-K FF truth table

How comes ?

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Edge-Triggered Flip-Flops (cont.)

Here is one example to test your understanding.

Consider only positive-edged of the clock pulse

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Edge-Triggered Flip-Flops (cont.)

One more example and try to figure out

by yourself !!

Set

Toggle

Set

Latch

CLK

J

K

Q

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Q

Edge-Triggered Flip-Flops (cont.)

Asynchronous Preset and Clear inputs

FF outputs are independent of the clock if either “Preset” or

“Clear” is asserted.

PRE

Q

J

CLK

K

CLR

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PRE

Q

CLR

Edge-Triggered Flip-Flops (cont.)

Check by yourself for this example !

Latch

Set

Toggle

Set

Reset

Toggle

PRE

CLK

Q

J

J

K

Set

CLK

Reset

K

Q

CLR

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FFs Operating Characteristics

Propagation delay time is specified for the rising and falling outputs. It is measured between the 50% level of the clock to the 50% level of the output transition.

50% point on triggering edge

CLK

CLK

50% point

50% point on HIGH-to- LOW transition of Q

Q

Q

50% point on LOW-to-HIGH transition of Q

tPLH

tPHL

The typical propagation delay time for the 74AHC family (CMOS) is 4 ns. Even faster logic is available for specialized applications.

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FFs Operating Characteristics (cont.)

Another propagation delay time specification is the time required for an asynchronous input to cause a change in the output. Again it is measured from the 50% levels. The 74AHC family has specified delay times under 5 ns.

50% point

CLR

50% point

PRE

Q

50% point

Q

50% point

tPHL

tPLH

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FFs Operating Characteristics (cont.)

Set-up time and hold time are times required before and after the clock transition that data must be present to be reliably clocked into the flip-flop.

D

Setup time is the minimum time for the data to be present before the clock.

CLK

Set-up time, ts

Hold time is the minimum time for the data to remain after the clock.

D

CLK

Hold time, tH

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FFs Operating Characteristics (cont.)
• Some other important characteristics are:-
• Maximum clock frequency
• Pulse widths
• Power dissipation
• Speed-power product

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FF Applications
• Parallel data storage
• Frequency division
• Counter (will be illustrated in detail later on)

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Q

FF Applications (cont.)

Output lines

Data storage

Q0

Data is stored until the next clock pulse.

Q1

PRE

Q

J

Q2

Parallel data input lines

CLK

Q3

K

Clock

CLR

Clear

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FF Applications (cont.)

For frequency division, it is simple to use a flip-flop in the toggle mode or to chain a series of toggle flip flops to continue to divide by two.

HIGH

HIGH

One flip-flop will divide fin by 2, two flip-flops will divide fin by 4 (and so on). A side benefit of frequency division is that the output has an exact 50% duty cycle.

QA

QB

fout

J

J

fin

CLK

CLK

K

K

fin

Waveforms:

fout

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Counter

Counting in binary.

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

LSB changes on every number.

The next bit changes on every fourth number.

The next bit changes on every other number.

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Counter (cont.)
• Counter can be formed by connecting FFs together
• Counter can be categorized into two cases, according to the ways they are clocked !!
• Asynchronous counter (ripple counter)
• Each FF formed counter do not change their states at the same time
• Synchronous counter
• Each FF in this counter is clocked concurrently.

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HIGH

Q0

Q1

Q2

J0

J1

J2

CLK

C

C

C

Q0

Q1

K0

K1

K2

Asynchronous Counters

Three bit asynchronous counter

In an asynchronous counter, the clock is applied only to the first stage. Subsequent stages derive the clock from the previous stage.

The three-bit asynchronous counter shown is typical. It uses J-K flip-flops in the toggle mode.

Waveforms are on the following slide…

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Asynchronous Counters (cont.)

Notice that the Q0 output is triggered on the leading edge of the clock signal. The following stage is triggered from Q0. The leading edge of Q0 is equivalent to the trailing edge of Q0. The resulting sequence is that of an 3-bit binary up counter.

CLK

Q0

Q1

Q2

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Asynchronous Counters (cont.)

Propagation delay

Asynchronous counters are sometimes called ripple counters, because the stages do not all change together. For certain applications requiring high clock rates, this is a major disadvantage.

CLK

Notice how delays are cumulative as each stage in a counter is clocked later than the previous stage.

Q0

Q1

Q2

Q0 is delayed by 1 propagation delay, Q2 by 2 delays and Q3 by 3 delays.

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HIGH

Q0

Q1

Q2

J0

J1

J2

CLK

C

C

C

Q0

Q1

K0

K1

K2

Asynchronous Counters (cont.)

The modulus of a counter is the number of output states it

goes through before returning its self back to zero.

The maximum possible number of states (maximum modulus)

of a counter is 2n

Counter with 3 FFs count from 0-7 and called modulo-8 counter.

Counters can be designed to have a number of states in their

sequences <2n.This type of sequence is called a

truncated sequence.

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HIGH

Q3

Q0

Q1

Q2

J0

J1

J2

J3

CLK

C

C

C

C

K0

K1

K2

K3

Asynchronous Counters (cont.)

This counter uses partial decoding to recycle the count sequence to zero after the 1001 state (modulo-10 counter).

CLR

Use the output of NAND gate

to clear input of the FFs

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Asynchronous Counters (cont.)

Asynchronous decade counter (cont.)

When Q1 and Q3 are HIGH together, the counter is cleared by a “glitch” on the CLR line.

CLK

Q0

Glitch

Q1

Q2

Q3

CLR

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Glitch

Asynchronous Counters (cont.)

The 74LS93A asynchronous counter

The 74LS93A has one independent toggle J-K flip-flop driven by CLK A and three toggle J-K flip-flops that form an asynchronous counter driven by CLK B.

The counter can be extended to form a 4-bit counter by connecting Q0 to the CLK B input. Two inputs are provided that clear the count.

CLK B

J0

J1

J2

J3

C

C

C

C

CLK A

K0

K1

K2

K3

All J and K inputs are connected internally HIGH

RO (1)

RO (2)

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Q3

Q0

Q1

Q2

Synchronous Counters

All flip-flops are clocked together with a common clock pulse.

Trade small propagation delays with more circuitry to control states changes.

Toggle mode

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Synchronous Counters (cont.)

Timing diagram of 2-bit synchronous counter

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Synchronous Counters (cont.)

3-bit binary synchronous counter

HIGH

Q0

Q0Q1

Q0

Q1

Q2

J0

J1

J2

C

C

C

K0

K1

K2

CLK

Timing diagram of 3-bit synchronous counter

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Synchronous Counters (cont.)

Analysis of synchronous counters (Tabular technique)

1. Put the counter in an arbitrary state; then determine the inputs for this state.

HIGH

Q0

Q0Q1

Q2

Q0

Q1

J0

J1

J2

2. Use the new inputs to determine the next state: Q2 and Q1 will latch and Q0 will toggle.

C

C

C

K0

K1

K2

3. Set up the next group of inputs from the current output.

CLK

Outputs

Logic for inputs

0 0 0

0

0

0

0

1

1

0 0 1

0

0

1

1

1

1

4. Q2 will latch again but both Q1 and Q0 will toggle.

0 1 0

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Synchronous Counters (cont.)

Analysis of synchronous counters (Tabular technique)

Outputs

Logic for inputs

0 0 0

0

0

0

0

1

1

0 0 1

0

0

1

1

1

1

0 1 0

0

0

0

0

1

1

0 1 1

1

1

1

1

1

1

1 0 0

1

1

0

0

0

0

1 0 1

0

0

1

1

1

1

1 1 0

0

0

0

0

1

1

1 1 1

1

1

1

1

1

1

0 0 0

At this points all states have been accounted for and the counter is ready to recycle…

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Synchronous Counters (cont.)

A 4-bit synchronous binary counter

The 4-bit binary counter has one more AND gate than the 3-bit counter just described. The shaded areas show where the AND gate outputs are HIGH causing the next FF to toggle.

Q0

Q1

Q2

Q3

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Synchronous Counters (cont.)

4-bit synchronous decade counter

With some additional logic, a binary counter can be converted to a BCD synchronous decade counter. After reaching the count 1001, the counter recycles to 0000.

This gate detects 1001, and causes FF3 to toggle on the next clock pulse. FF0 toggles on every clock pulse. Thus, the count starts over at 0000.

Q3

Q0

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Synchronous Counters (cont.)

Waveforms for the decade counter:

CLK

Q0

Q1

Q2

Q3

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Synchronous Counters (cont.)

A 4-bit synchronous binary counter in IC form

The 74LS163 is a 4-bit IC synchronous counter with additional features over a basic counter. It has parallel load, a CLR input, two chip enables, and a ripple count output that signals when the count has reached the terminal count.

Data inputs

D0

D1

D2

D3

(Ripple Clock Output)

goes high when count to

state 15

CLR

ENT

RCO

ENP

CLK

Both enable I/Ps

Q0

Q1

Q2

Q3

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Data outputs

Synchronous Counters (cont.)

CLR

D0

D1

Data inputs

D2

D3

CLK

ENP

ENT

Q0

Q1

Data outputs

Q2

Q3

RCO

12 13 14 15 0 1 2

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Count Inhibit

Clear Preset

Down/ Q2 changes states

when Q1&Q0=0

Down/ Q1 changes states

when Q0=0

Always toggle,

hence J0=K0 =1

Up/ Q2 changes states

when Q1&Q0=1

Up/ Q1 changes states

when Q0=1

Up/Down Synchronous Counters
• Counting in either direction (also called a bi-directional counter)

Says if u’d like to design a 3-bit up/down counter

Up

Q2

Q1

Q0

Down

Clock pulse

0

1

2

3

4

5

6

7

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

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Up/Down Synchronous Counters (cont.)

UP

HIGH

FF0

FF1

FF2

Q2

J0

J1

J2

Q0

Q1

UP/DOWN

C

C

C

Q0

Q1

Q2

K0

K1

K2

DOWN

Q0.DOWN

CLK

Basic 3-bit up/down synchronous counter

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D0

D1

D2

D3

Data inputs

74HC190

The 74HC190 is a high speed CMOS synchronous up/down decade counter with parallel load capability. It also has a active LOW ripple clock output (RCO) and a MAX/MIN output when the terminal count is reached.

MAX/MIN

CTR DIV 10

RCO

C

CLK

CTEN

CTEN

Q0

Q1

Q2

Q3

Data outputs

D0

D1

D2

D3

Data inputs

D/U

D/U

74HC191

MAX/MIN

CTR DIV 16

RCO

C

CLK

Q0

Q1

Q2

Q3

Data outputs

Up/Down Synchronous Counters (cont.)

The 74HC191 has the same inputs and outputs but is a synchronous up/down binary counter.

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Design of Synchronous Counters

General model of a sequential circuit

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Design of Synchronous Counters (cont.)

Design procedure for synchronous counters

Step I: State diagram

Step II: Next state table:

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Design of Synchronous Counters (cont.)

Step III: FF transition table

The J-K transition table lists all combinations of present output (QN) and next output (QN+1) on the left. The inputs that produce that transition are listed on the right.

Each time a flip-flop is clocked, the J and K inputs required for that transition are mapped onto a K-map.

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Design of Synchronous Counters (cont.)

Step IV: K-maps

Example of mapping procedure

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Design of Synchronous Counters (cont.)

Step IV: K-maps (cont.)

K-maps for present-state J&K inputs

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Design of Synchronous Counters (cont.)

Step V: Logic expressions

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Design of Synchronous Counters (cont.)

Step VI: Counter implementation

FF0

FF1

FF2

Q2

J0

J1

J2

Q0

Q1

C

C

C

Q0

Q1

Q2

K0

K1

K2

CLK

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Cascading is a method of achieving higher-modulus counters. For synchronous IC counters, the next counter is enabled only when the terminal count of the previous stage is reached.

Two cascaded asynchronous counter

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Timing diagram

HIGH

Counter 2

Counter 1

CTEN

TC

CTEN

TC

CTR DIV 16

CTR DIV 16

CLK

C

Q2

Q0

Q1

Q3

C

Q2

Q0

Q1

Q3

fin

fout

Modulus-256 synchronous counter using two cascaded synchronous counters

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Counter Decoding

Decoding is the detection of a binary number and can be done with an AND gate.

Question

1.What number is decoded by this gate?

2. How to modify it in order to provide active-LOW decoding?

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Counter Decoding (cont.)

Decoding glitches

BCD counter and decoder

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Counter Decoding (cont.)

Way to eliminate glitches

BCD counter and decoder with strobing

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Counter Applications

Digital clocks

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Hours Counter

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Counter Applications (cont.)

Automobile parking control

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Basic Shift Register Functions
• A shift register is an arrangement of flip-flops with important applications in storage and movement of data.

Data in

Data in

Data out

Data out

Data in

Data out

Serial in/shift right/serial out

Serial in/shift left/serial out

Parallel in/serial out

Data in

Data in

Data out

Data out

Rotate right

Rotate left

Serial in/parallel out

Parallel in/parallel out

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1

1

1

1

1

CLK

Serial-in/Serial out Shift Register
• 5-bit serial in/serial out shift register implemented with D flip-flops.

1

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CLK

CLK

CLK

CLK

Serial In/Parallel Out Shift Registers
• 4-bit serial in/parallel out shift register
• For example, assume the binary number 1011 is loaded sequentially, one bit at each clock pulse.

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74HC164A Shift Register
• 8-bit serial in/parallel out shift register
• One of the two serial data inputs may be used as an active HIGH enable to gate the other input.
• If no enable is needed, the other serial input can be connected to Vcc.
• The 74HC164A has an active LOW asynchronous clear.
• Data is entered on the leading-edge of the clock.

CLR

CLK

A

Serial inputs

B

Q3

Q7

Q0

Q1

Q2

Q4

Q5

Q6

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B acts as an active HIGH enable for the data on A.

As with CMOS devices, unused inputs should always be connected to a logic level; unused outputs should be left open.

Waveforms for the 74HC164A

CLR

A

Serial inputs

B

CLK

Q0

Q1

Q2

Q3

Outputs

Q4

Q5

Q6

Q7

Clear

Clear

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Parallel In/Serial Out Shift Registers
• Shift registers can be used to convert parallel data to serial form.

D3

D0

D1

D2

Serial data out

Q3

Q0

Q1

Q2

CLK

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74HC165 Shift Register
• 8-bit parallel in/serial out shift register
• The clock (CLK) and clock inhibit (CLK INH) lines are connected to a common OR gate, so either of these inputs can be used as an active-LOW clock enable with the other as the clock input.
• Data is loaded asynchronously when SH/LD is LOW and moved through the register synchronously when

SH/LD is HIGH and a rising clock pulse occurs.

D0

D1

D2

D3

D4

D5

D6

D7

Q7

SH/LD

SER

CLK INH

Q7

CLK

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74HC165 (cont.)

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Bidirectional Shift Register
• Bidirectional shift registers can shift the data in either direction using a RIGHT/LEFT input.

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Example
• How will the pattern change if the RIGHT/LEFT control signal is inverted?

CLK

Shift left

RIGHT/LEFT

Shift right

Serial data in

Q0

Q1

Q2

Q3

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Example (cont.)

CLK

Shift left

RIGHT/LEFT

Shift right

Shift right

Shift left

Serial data in

Q0

Q1

Q2

Q3

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Universal Shift Register

A universal shift register has both serial and parallel input and output capability. The 74HC194 is an example of a 4-bit bidirectional universal shift register.

D0

D1

D2

D3

CLR

S0

S1

SR SER

SL SER

CLK

Q0

Q1

Q2

Q3

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Sample Waveforms

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Shift Register Counters
• Shift registers can form useful counters by recirculating a pattern of 0’s and 1’s. Two important shift register counters are the Johnson counter and the ring counter.
• The Johnson counter can be made with a series of either D flip-flops or J-K flip-flops.

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Johnson counter
• The Johnson counter is useful when you need a sequence that changes by only one bit at a time but it has a limited number of states (2n, where n = number of stages).

The first five counts for a 4-bit Johnson counter that is initially cleared are:CLK Q0Q1Q2Q3

0

1

2

3

4

5

6

7

0 0 0 0

1 0 0 0

1 1 0 0

1 1 1 0

1 1 1 1

0 1 1 1

0 0 1 1

0 0 0 1

Question

What are the remaining 3 states?

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Ring Counter
• The ring counter can also be implemented with either D flip-flops or J-K flip-flops.
• 4-bit ring counters are constructed from a series of D flip-flops and J-K flip-flops. Notice the feedback.

Question

Describe the disadvantage and advantage of the ring counter?

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Ring Counter
• A common pattern for a ring counter is to load it with a single 1 or a single 0. The waveforms shown here are for an 8-bit ring counter with a single 1.

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Shift Register Applications
• Examples: Time Delay, Parallel/Serial Data Converter, and Keyboard Encoder

An 8-bit serial in/serial out shift register has a 40 MHz clock. What is the total delay through the register?

Example

Solution

The delay for each clock is 1/40 MHz = 25 ns

25 ns

The total delay is 8 x 25 ns =200 ns

= 200 ns

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Start

Bit (0)

Stop Bits (1)

Parallel/Serial Data Converter

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UART
• A UART (Universal Asynchronous Receiver Transmitter) is a serial-to-parallel converter and a parallel to serial converter.
• UARTs are commonly used in small systems where one device must communicate with another. Parallel data is converted to asynchronous serial form and transmitted.

Data bus

CLK

CLK

Serial data out

Serial data in

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Keyboard Encoder
• The keyboard encoder is an example of where a ring counter is used in a small system to encode a key press.
• Two 74HC195 shift registers are connected as an 8-bit ring counter preloaded with a single 0.
• As the 0 circulate in the ring counter, it “scans” the keyboard looking for any row that has a key closure.
• When one is found, a corresponding column line is connected to that row line.

241-208 CH9

Conclusion
• ET FFs is a synchronous bistable device, whose state depends on the input only at the triggering transition of a clock pulse
• JK-FFs is mostly used since we can design other FF types (D,RS) with JK-FF.
• Applications of FFs are frequency division, counter, and storage device.

241-208 CH7