saleem sabbagh najeeb darawshy supervisors mony orbach technion ilia averbouch ibm n.
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FPGA Based SAT Solver. Saleem Sabbagh & Najeeb Darawshy Supervisors: Mony Orbach, Technion & Ilia Averbouch, IBM. Final presentation. Started at: Winter 2012 Duration: Semester. outline. What is SAT Reminder - description and goals Flow diagram Circuit diagram

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saleem sabbagh najeeb darawshy supervisors mony orbach technion ilia averbouch ibm

FPGA Based SAT Solver

Saleem Sabbagh & Najeeb Darawshy

Supervisors: Mony Orbach, Technion &

Ilia Averbouch, IBM

Final presentation

Started at: Winter 2012

Duration: Semester

outline
outline
  • What is SAT
  • Reminder - description and goals
  • Flow diagram
  • Circuit diagram
  • Example simulation results
  • Live Presentation
  • Runtimes
  • Compilation times
  • Notes & Conclusions
  • What’s Next
what is sat
What is sat
  • Boolean Satisfiability Problem
  • Given a Boolean propositional formula, does there exist assignment of values such that the formula becomes true?
  • e.g., given the formula

f=(x1 ˅ x3˅ -x4) ˄ (x4) ˄ (x2 ˅ -x3)

are there values of x1,x2,x3,x4 that produce f=‘1’

reminder description and goals
Reminder – description and goals
  • Description:
    • Hardware based SAT Solver
  • Goals:
    • Implementing SAT instances into FPGA
    • Measuring build and run times for benchmark examples
    • Enabling further development of fast hardware based SAT Solver
flow diagram
Flow diagram

Programmable File

Circuit Description as VHDL

CNF Instances

Synthesis

Conversion

Device

Programmer

FPGA

Running

SAT Solver

PC

DE2

Analysis and Timing

Report

circuit diagram
circuit diagram

F

clk

en

sOUT

timeOUT

circuit diagram lfsr
circuit diagram - LFSR
  • LFSR Random Generator (Generic width up to 168 bits)
circuit diagram smartshift
circuit diagram - Smartshift
  • A right shift register with Parallel Load, Shift Enable, Parallel and Serial output
  • While SAT still unsatisfiable F=0, NOT(F)=1 therefor:

LOAD=1  D is loaded into register;

SE=0  Shift not enabled.

  • When found satisfying input F=1, NOT(F)=0 therefor:

LOAD=0  Stop Loading Parallel input;

SE=1  Start shifting;

MSB  Satisfying input.

example simulation results
Example simulation results
  • For SAT instance of 20 variables and 91 clauses
    • Satisfying input: 00101011011101000000
runtime
Runtime

*Clock frequency is 50M [Hz]

compilation times
Compilation times

*Clock frequency is 50M [Hz]

compilation times analysis
Compilation times - Analysis
  • Compilation time is comprised of two main stages, Analysis & Synthesis and Place & Route. We found the problem to be associated directly to the peak interconnect usage during Place & Route stage.
notes
Notes
  • Tried several solutions for 1000-variables SAT with 4250 clauses in order to decrease compilation time:
    • Low Priority Optimization during Compliation – Did not help.
    • Better Altera board, Altera Stratix V – 85% cut in compilation time.
  • In order to better sample our variables spectrum, We have used two applications:
    • Java based Random SAT generator with 4.25:1 ratio (Clauses:Variables) which was used for compilation time analysis.
    • Cpp based satisfyable/unsatisfyable SAT generator used in official sat competitions which was used for runtimes analysis.
whats next
Whats next
  • Two approaches
    • Improving runtimes by designing smart sat solver instead of inefficient LFSR random generator
    • Improving compilation times by:
      • Understanding Altera compilation algorithms to enable faster SAT-specific fpga ready files.
      • Smart use of memory on FPGA to implement SAT.
slide15
Thank you!
  • Questions?