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Module 1: Introduction Topic 2: Trends & Challenges. OGI EE564 Howard Heck. Where Are We?. Introduction Overview Trends & Challenges Interconnect Technology Transmission Line Basics Analysis Tools Metrics & Methodology Advanced Transmission Lines Multi-Gb/s Signaling Special Topics.

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Presentation Transcript
where are we
Where Are We?
  • Introduction
    • Overview
    • Trends & Challenges
    • Interconnect Technology
  • Transmission Line Basics
  • Analysis Tools
  • Metrics & Methodology
  • Advanced Transmission Lines
  • Multi-Gb/s Signaling
  • Special Topics

Section 1.2

contents
Contents
  • Moore’s Law & Its’ Impact On Interconnect Design
  • System Architecture Evolution
  • Bus Scaling
    • System Bus
    • Cache Bus
    • Memory Bus
    • I/O Buses
  • Cost Constraints
  • Summary
  • References
  • Appendix: Scaling Trends

Section 1.2

moore s law
Moore’s Law
  • Moore’s Law: Silicon integration doubles every 2 years.
    • Application to microprocessors: Processor performance doubles every two years.
  • How is the performance growth achieved?
    • Frequency scaling: smaller, faster devices
    • Increased parallelism (e.g. pipelines, superscalar): more devices
    • Increased function (e.g. floating point, MMX): more devices
  • So What? Moore’s law impacts interconnect.
    • Higher frequency processors demand more data to keep functional units occupied doing useful work.
    • This means more wires operating at higher frequency.

Section 1.2

cpu performance trend frequency
CPU Performance Trend (Frequency)

Historically, 1 megabyte/second of data is supplied for each CPU MHz.

Section 1.2

pc architecture performance evolution
PC Architecture & Performance Evolution

486DX2 Processor (~1992)

  • 3 major buses
  • 33 MHz max frequency
  • 4 byte bus width

Pentium® 4 Processor (2003)

  • 4 major buses
  • 66 - 800 MHz
  • 4-16 byte widths

Section 1.2

pc architecture performance evolution7
PC Architecture & Performance Evolution

Core® 2 Processor (2008)

Section 1.2

bus performance trends
Bus Performance Trends

System Bus

System Bus Frequency

10000

8080

8085

8086

8088

1000

80186

80286

80386

486DX

100

Frequency [MHz]

486DX2

486DX4

Pentium®

Pentium® Pro

Pentium® II

10

Celeron®

Pentium® III

Pentium® 4

Pentium® 4EE

1

1970

1975

1980

1985

1990

1995

2000

2005

2010

Year

The CPU bus follows Moore’s Law, too.

Section 1.2

bus performance trends9
Bus Performance Trends

Memory

  • SOA (2008):
  • 1600 MHz
  • 25,600 MB/s

Section 1.2

cost constraints
Cost Constraints

Motherboard& Connectors(< 5% of total)

O/S

Fax/Modem

CDROM

Case

Sound +

Memory

Speakers

Hard Disk

CPU

Monitor +

Video Card

Power Supply

Motherboard

Components

Approximate Cost Breakdown of a Desktop PC

  • Interconnect makes up <5% of the system cost.
    • Most technical problems can be solved with $.
    • High volume PC market can’t afford extra cost. The trend is toward even lower costs.
  • Designing Multi-GHz interconnects to fit in sub $1000 PCs is a huge challenge.

Section 1.2

summary
Summary
  • Moore’s law predicts the rate of growth of microprocessor performance. This growth drives increased interconnect performance requirements.
  • Interconnect designers are confronted with the challenges (opportunities) created by the demand for performance and the cost constraints of commodity computing.
    • Sales volume of PC system drops off sharply when the price exceeds the volume desktop price barrier.
    • System performance and function increase over time while selling price is decreasing.
    • Interconnect components account for < 5% of system cost.
    • Interconnect engineers must satisfy increased performance demands without increasing the cost of the solution.

Section 1.2

references
References

The data contained in the graphs was gathered from numerous sources, including:

8086/80286/80386/80486

  • Component Data Catalog, Intel Corporation, 1980.
  • Microprocessors, Volume 1, Intel Corporation, 1992.
  • Intel486TM Microprocessors and Related Products, Intel Corporation, 1995.

Pentium Processor

  • PentiumTM Processors and Related Products, Intel Corporation, 1995.
  • Pentium Processor, Intel Corporation, June 1997, Order Number 241997-010, http://developer.intel.com/design/pentium/datashts/241991.htm.
  • Pentium Processor with MMXTM Technology, Intel Corporation, June 1997, Order Number 243185-005, http://download.intel.com/design/MMX/datashts/24318504.pdf.
  • Pentium Processor Performance Brief, Intel Corporation, June 1997, Order Number 241557-010, http://download.intel.com/design/pentium/perfbref/24155710.pdf.

Section 1.2

references 2
References #2

Pentium Pro Processor

  • Pentium Pro Processor Performance Brief, Intel Corporation, June 1997, Order Number 242768-006.

Pentium II Processor

  • Pentium II Processor at 333 MHz, 300 MHz, 266 MHz, and 233 MHz, Intel Corporation, January 1998, Order Number 243335-003, http://developer.intel.com/PentiumII/datashts/243335.htm.
  • Pentium II Processor at 350 MHz, 400 MHz, and 450 MHz, Intel Corporation, August 1998, Order Number 243657-003, http://developer.intel.com/PentiumII/datashts/243657.htm.
  • Pentium II Processor Performance Brief, Intel Corporation, August 1998, Order Number 243336-006, http://developer.intel.com/procs/perf/doc/pii_august.htm.
  • Pentium II Processor Developer’s Manual, Intel Corporation, October 1997, Order Number 243502-001, ftp://download.intel.com/design/PentiumII/manuals/24350201.pdf.

Section 1.2

references 3
References #3

Intel CeleronTM Processor

  • Intel Celeron Processor at 266 MHz, 300 MHz, 300A MHz, and 333 MHz, Intel Corporation, November 1998, Order Number 2436558-004, http://developer.intel.com/design/celeron/datashts/243658.htm.
  • Intel Celeron Processor Performance Brief, Intel Corporation, August 1998, Order Number 243706-003, http://developer.intel.com/procs/perf/doc/celeron_august.htm.

System Technologies

  • Data regarding memory bandwidth metrics was provided by George Vergis of Intel Corporation.
  • Meeting System Demands with Synchronous DRAM Technology, Texas Instruments, http://www.ti.com/sc/docs/memory/brief.html.
  • Memory Latency Comparison, Rambus Inc., 1996.
  • Rambus Memory: Multi-Gigabytes/Second and Minimum System Cost, Rambus, Inc., 1997.
  • Synchronous DRAMs: The DRAM of the Future, IBM Microelectronics Division, 1997.

Section 1.2

pc architecture 80486 generation 1992
PC Architecture: 80486 Generation (~1992)
  • 3 major buses
  • 33 MHz maximum frequency

Section 1.2

pc architecture pentium 1996
PC Architecture: Pentium® (~1996)
  • 3 major buses
  • 66 MHz maximum frequency
  • 64 bit bus width

Section 1.2

pc architecture pentium ii 1997
PC Architecture: Pentium® II (~1997)
  • 5 major buses
  • 133/150 MHz
  • 64 bits

Section 1.2

pc architecture pentium ii 1998
PC Architecture: Pentium® II (~1998)
  • 5 major buses
  • 100/133/225 MHz
  • 64 bits

Section 1.2

pc architecture pentium iii 1999 2000
PC Architecture: Pentium® III (~1999-2000)
  • 4 major buses
  • 133/266/800 MHz
  • 16-64 bits

Section 1.2

pc architecture pentium 4 2000
PC Architecture: Pentium® 4 (2000)
  • 4 major buses
  • 133/266/800 MHz
  • 32-64 bits

Section 1.2

pc architecture pentium 4 2002
PC Architecture: Pentium® 4 (2002)
  • 4 major buses
  • 133/266/800 MHz
  • 32-64 bits

Section 1.2