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Lecture 13 PicoBlaze I/O & Interrupt Interface Example of Assembly Language Routine. ECE 448 – FPGA and ASIC Design with VHDL. Required reading. P. Chu, FPGA Prototyping by VHDL Examples Chapter 16, PicoBlaze I/O Interface Chapter 17, PicoBlaze Interrupt Interface.

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lecture 13 picoblaze i o interrupt interface example of assembly language routine

Lecture 13PicoBlaze I/O & Interrupt InterfaceExample ofAssembly Language Routine

ECE 448 – FPGA and ASIC Design with VHDL

required reading
Required reading
  • P. Chu, FPGA Prototyping by VHDL Examples
    • Chapter 16, PicoBlaze I/O Interface
    • Chapter 17, PicoBlaze Interrupt Interface

ECE 448 – FPGA and ASIC Design with VHDL

output decoding of four output registers
Output Decoding of Four Output Registers

ECE 448 – FPGA and ASIC Design with VHDL

timing diagram of an output instruction
Timing Diagram of an Output Instruction

ECE 448 – FPGA and ASIC Design with VHDL

truth table of a decoding circuit
Truth Table of a Decoding Circuit

ECE 448 – FPGA and ASIC Design with VHDL

block diagram of four continuous access ports
Block Diagram of Four Continuous-Access Ports

ECE 448 – FPGA and ASIC Design with VHDL

timing diagram of an input instruction
Timing Diagram of an Input Instruction

ECE 448 – FPGA and ASIC Design with VHDL

block diagram of four single access ports
Block Diagram of Four Single-Access Ports

ECE 448 – FPGA and ASIC Design with VHDL

fifo interface
FIFO Interface

clk

rst

rst

clk

FIFO

dout

din

8

8

empty

full

write

read

ECE 448 – FPGA and ASIC Design with VHDL

operation of fifo
Operation of FIFO

ECE 448 – FPGA and ASIC Design with VHDL

interrupt flow
Interrupt Flow

ECE 448 – FPGA and ASIC Design with VHDL

timing diagram of an interrupt event
Timing Diagram of an Interrupt Event

ECE 448 – FPGA and ASIC Design with VHDL

interrupt interface with a single event
Interrupt Interface with a Single Event

ECE 448 – FPGA and ASIC Design with VHDL

interrupt interface with two requests
Interrupt Interface with Two Requests

ECE 448 – FPGA and ASIC Design with VHDL

time multiplexed seven segment display
Time-Multiplexed Seven Segment Display

ECE 448 – FPGA and ASIC Design with VHDL

block diagram of the hexadecimal time multiplexing circuit
Block Diagram of the Hexadecimal Time-Multiplexing Circuit

ECE 448 – FPGA and ASIC Design with VHDL

hexadecimal multiplexing circuit based on picoblaze and mod 500 counter
Hexadecimal Multiplexing Circuit Based on PicoBlaze and mod-500 Counter

ECE 448 – FPGA and ASIC Design with VHDL

example of a function in the picoblaze assembly language

Example ofa function in the PicoBlazeassembly language

ECE 448 – FPGA and ASIC Design with VHDL

slide20

Notation

a Multiplicand ak-1ak-2 . . . a1 a0

x Multiplier xk-1xk-2 . . . x1 x0

p Product (a  x) p2k-1p2k-2 . . . p2 p1 p0

slide21

Multiplication of two 4-bit unsigned

binarynumbers

Partial Product 0

Partial Product 1

Partial Product 2

Partial Product 3

slide22

Unsigned Multiplication – Basic Equations

k-1

x = xi  2i

p = a  x

i=0

k-1

p = a  x = a  xi  2i =

= x0a20 + x1a21 + x2a22 + … + xk-1a2k-1

i=0

slide23

Iterative Algorithm for Unsigned Multiplication

Shift/Add Algorithm

p = a  x = x0a20 + x1a21 + x2a22 + … + xk-1a2k-1

=

= (...((0 + x0a2k)/2 + x1a2k)/2 + ... + xk-1a2k)/2 =

k times

p(0) = 0

j=0..k-1

p(j+1) = (p(j) + xj a 2k) / 2

p = p(k)

slide24

Unsigned Multiplication Computations

8 bits

8 bits

pL

pH

p

p(j)

xj a

+ xj a 28

+

pL

pH

C

2 p(j+1)

>> 1

p(j+1)

pL

pH

C

pH = s5

pL = s6

PicoBlaze Registers

a = s3

x = s4

slide25

Unsigned Multiplication Subroutine (1)

;=========================================================

; routine: mult_soft

; function: 8-bit unsigned multiplier using

; shift-and-add algorithm

; input register:

; s3: multiplicand

; s4: multiplier

; output register:

; s5: upper byte of product

; s6: lower byte of product

; temporary register:

; s2: index j

;=========================================================

slide26

Unsigned Multiplication Subroutine (2)

mult_soft:

load s5, 00 ;clear s5

load s2, 08 ;initialize loop index

mult_loop:

sr0 s4 ;shift lsb to carry

jump nc, shift_prod ;lsb is 0

add s5, s3 ;lsb is 1

shift_prod:

sra s5 ;shift upper byte right,

;carry to MSB, LSB to carry

sra s6 ;shift lower byte right,

;lsb of s5 to MSB of s6

sub s2, 01 ;dec loop index

jump nz, mult_loop ;repeat until i=0

return

slide27

Edit instructions - Shifts

*All shift instructions affect Zero and Carry flags

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