ECE 331 – Digital System Design

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ECE 331 – Digital System Design. Multi-level Logic Circuits and NAND-NAND and NOR-NOR Circuits (Lecture #8). The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition , by Roth and Kinney,

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ECE 331 – Digital System Design

Multi-level Logic Circuits

and

NAND-NAND and NOR-NOR Circuits

(Lecture #8)

The slides included herein were taken from the materials accompanying

Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,

and were used with permission from Cengage Learning.

ECE 331 - Digital System Design

Multi-level Logic Circuits

ECE 331 - Digital System DesignMulti-level Logic Circuits

Thus far we have focused on the realization of optimal logic circuits through the derivation of

Minimum Sum-of-Products expressions

Minimum Product-of-Sums expressions

Both forms of Boolean expressions are realized as two-level logic circuits

AND-OR circuit ↔ SOP

OR-AND circuit ↔ POS

There are a maximum of two logic gates between every input and the output(s).

ECE 331 - Digital System DesignMulti-level Logic Circuits

A two-level logic circuit is usually efficient for Boolean expressions of a few variables.

However, as the number of inputs increases, a two-level logic circuit may encounter in fan-in problems.

Fan-in refers to the number of inputs to a logic gate

Whether fan-in is an issue is dependent upon the technology used to implement the logic circuit.

Standard TTL and CMOS chips

Field Programmable Gate Array (FPGA)

Complex Programmable Logic Device (CPLD)

ECE 331 - Digital System DesignMulti-level Logic Circuits

May require fewer logic gates than the logically equivalent two-level logic circuit.

Reduced (silicon) area

Decreased cost

May require less complex wiring between logic gates

Fewer literals results in fewer interconnecting wires

Has a greater propagation delay than the logically equivalent two-level logic circuit.

Decreased speed

ECE 331 - Digital System DesignMulti-level Logic Circuits

Example:

Find a circuit of AND and OR gates to realize

f (a, b, c, d) = Ʃ m(1, 5, 6, 10, 13, 14)

Consider solutions with two levels of gates and three levels of gates. Try to minimize the number of gates and the total number of gate inputs. Assume that all variables and their complements are available as inputs.

ECE 331 - Digital System DesignMulti-level Logic Circuits

Example:

First, simplify f by using a Karnaugh map.

Minimum SOP

Minimum POS

ECE 331 - Digital System DesignMulti-level Logic Circuit

Example:

This leads directly to a two-level AND-OR logic circuit for the minimum SOP expression.

ECE 331 - Digital System DesignMulti-level Logic Circuit

Example:

And leads directly to a two-level OR-AND logic circuit for the minimum POS expression.

ECE 331 - Digital System DesignMulti-level Logic Circuit

Example:

Factoring the minimum SOP expression yields:

f = c'd.(a' + b) + cd'.(a + b)

Which leads to the three-level OR-AND-OR logic circuit:

ECE 331 - Digital System DesignMulti-level Logic Circuit

Example:

To get a three-level circuit with an AND gate output, we partially multiply out the POS expression using (X + Y)(X + Z) = X + Y Z:

f= [c + d(a′ + b)][c′ + d′(a + b)]

This would require four levels of gates to realize; however, if we multiply out d′(a + b) and d(a′ + b), we get

f= (c + a′d + bd)(c′ + ad′ + bd′)

ECE 331 - Digital System DesignMulti-level Logic Circuit

Example:

Which leads to the three-level AND-OR-AND logic circuit:

Multi-level Logic Circuits

For this particular example, the best two-level solution had an AND gate at the output, and the best three-level solution had an OR gate at the output. In general, to be sure of obtaining a minimum solution, one must find both the circuit with the AND-gate output and the one with the OR-gate output.

ECE 331 - Digital System Design

NAND-NAND and NOR-NOR Circuits

ECE 331 - Digital System DesignLogic Gates

AND and OR Gates

2-input gates realized with 6 CMOS transistors

3-input gates realized with 8 CMOS transistors

NAND and NOR Gates

2-input gates realized with 4 CMOS transistors

3-input gates realized with 6 CMOS transistors

More cost efficient to design logic circuits using NAND and NOR gates.

ECE 331 - Digital System DesignNAND and NOR Gates

F= (A + B + C)′ = A′B′C′

F = (ABC)′ = A′ + B′ + C′

ECE 331 - Digital System DesignNAND Gate

Any logic function can be realized using only NAND gates. Consequently, it is said to be a functionally complete set of gates.

ECE 331 - Digital System DesignNOR Gate

Any logic function can be realized using only NOR gates. Consequently, it, too, is said to be a functionally complete set of gates.

ECE 331 - Digital System DesignNAND-NAND and NOR-NOR Circuits

A two-level circuit composed of AND and OR gates is easily converted to a circuit composed of NAND or NOR gates only.

Use F = (F′)′ and then apply DeMorgan′s laws:

(X1 + X2 + … + Xn)′ = X1′ X2′…Xn′

(X1 X2…Xn)′ = X1′ + X2′ + … + Xn′

ECE 331 - Digital System DesignNAND-NAND Circuits

Example:

Convert the minimum sum-of-products (AND-OR) form to the equivalent NAND-NAND form.

F= A + BC′ + B′CD = [(A + BC′ + B′CD)′ ]′

Solution:

F= A + BC′ + B′CD = [A′ •(BC′)′• (B′CD)′]′

ECE 331 - Digital System DesignNOR-NOR Circuits

Example:

Convert the minimum product-of-sums (OR-AND) form to the equivalent NOR-NOR form.

F= (A + B+ C)(A + B′ + C')(A +C' +D)

= {[(A + B + C)(A + B′ + C′)(A + C′ + D)]′ }′

Solution:

F = [(A + B + C)′ + (A + B′ + C′)′ + (A + C′ + D)′]′

ECE 331 - Digital System DesignDesign of NAND-NAND Circuits

Find a minimum SOP expression for f.

Draw the corresponding AND-OR circuit.

Replace all gates with NAND gates, leaving the gate interconnection unchanged.

If the output gate has any single literals as inputs, complement these literals.

ECE 331 - Digital System DesignDesign of NOR-NOR Circuits

Find a minimum POS expression for f.

Draw the corresponding OR-AND circuit.

Replace all gates with NOR gates, leaving the gate interconnection unchanged.

If the output gate has any single literals as inputs, complement these literals.

Design of Multi-level NAND-Gate Circuits

Simplify the switching function to be realized.

Design a multi-level circuit of AND and OR gates.

The output gate must be an OR gate.

The gates must alternate: AND, OR, AND, OR, …

Number the levels starting with the output gate.

The output gate is level 1.

Replace all gates with NAND gates, leaving interconnections between gates unchanged.

Leave inputs to gates at levels 2, 4, 6, … unchanged; invert literals that appear as inputs to gates at levels 1, 3, 5, …

Design of Multi-level NOR-Gate Circuits

Simplify the switching function to be realized.

Design a multi-level circuit of AND and OR gates.

The output gate must be an AND gate.

The gates must alternate: OR, AND, OR, AND, …

Number the levels starting with the output gate.

The output gate is level 1.

Replace all gates with NOR gates, leaving interconnections between gates unchanged.

Leave inputs to gates at levels 2, 4, 6, … unchanged; invert literals that appear as inputs to gates at levels 1, 3, 5, …

Alternate Logic Gate Symbols

Logic designers who design complex digital systems often find it convenient to use more than one representation for a given type of gate.

inverter

ECE 331 - Digital System Design

Multiple-output Circuits

ECE 331 - Digital System Design

Review the material provided in the textbook.

(Sections 7.6 – 7.7)

Multiple-output Logic Circuits