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Silicon on Insulator MOSFET Technology: Design and Evolution of the Modern SOI Fully-depleted MOSFET. Presented By: Aniket A. Breed/ Dr. Marc Cahay Department of Electrical and Computer Engineering and Computer Science. Semiconductor Devices Laboratory. SOI – The technology of the future.

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silicon on insulator mosfet technology design and evolution of the modern soi fully depleted mosfet

Silicon on Insulator MOSFET Technology:Design and Evolution of the Modern SOI Fully-depleted MOSFET

Presented By:

Aniket A. Breed/ Dr. Marc Cahay

Department of Electrical and Computer Engineering and Computer Science.

Semiconductor Devices Laboratory

soi the technology of the future
SOI – The technology of the future.

Welcome to the world of Silicon On Insulator

Highlights

  • Reduced junction capacitance.
  • Absence of latchup.
  • Ease in scaling (buried oxide need not be scaled).
  • Compatible with conventional Silicon processing.
  • Sometimes requires fewer steps to fabricate.
  • Reduced leakage.
  • Improvement in the soft error rate.

Drawbacks

  • Drain Current Overshoot.
  • Kink effect
  • Thickness control (fully depleted operation).
  • Surface states.
the m etal o xide s emiconductor f ield e ffect t ransistor mosfet
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)

In layman terms, MOSFET acts like a switch

a historical perspective
A Historical Perspective

Moore’s Law

  • Number of Transistors on an integrated circuit chip doubles every 1.5 years.

(Courtesy: Intel© Corporation)

motivation
Motivation
  • Silicon-only planar transistors are fast approaching their scaling limit.
  • Short channel effects limiting scaling into sub nanometer regime.
  • Oxide thickness cannot be scaled down further, problems of tunneling.
  • Need to keep Silicon technology as the base technology while innovating future devices; cost is an important factor.
  • Performance and power dissipation need to be improved.
  • Smaller is faster !!
mosfet scaling trends
MOSFET Scaling Trends

Courtesy: Hewlett-Packard Labs

slide7

Planar MOSFET Scaling (Short-Channel Effect)

Lg = 0.35 m, Tox = 8 nm

Lg = 0.18 m, Tox = 4.5 nm

Short-Channel Effect

Short-Channel Effect

Lg = 0.07 m, Tox = 1.9 nm

Lg = 0.10 m, Tox = 2.5 nm

what after the planar mosfet alternative approaches
What After the Planar MOSFET (Alternative Approaches)

Strained Silicon Approach

Silicon-on-Insulator (SOI) Approach

  • Silicon grown on a layer of relaxed material like SiGe which has a near similar lattice constant as that of Silicon.
  • Strain induced in Silicon results in an improvement in the mobility, hence results in faster devices.
  • Silicon channel layer grown on a layer of oxide.
  • Absence of junction capacitance makes this an attractive option.
  • Low leakage currents and compatible fabrication technology.
classification of soi mosfets
Classification of SOI MOSFETs

Fully depleted SOI MOSFET

Partially depleted SOI MOSFET

Conventional MOSFET

  • Silicon film thickness greater than bulk depletion width for a partially-depleted MOSFET and less than the gate depletion width for a fully-depleted MOSFET.
  • Partially depleted MOSFETs often plagued by KINK effects, fully depleted devices virtually free from such effects.
  • Partially depleted devices can be faster than fully depleted devices under certain operating conditions.
illustration of the kink effect partially depleted structures
Illustration of the “Kink” effect (Partially depleted structures)

Partially depleted MOSFET

Fully depleted MOSFET

Kink effect is an intricate, yet undesirable phenomenon.

why multi gate soi mosfets
Why Multi-Gate SOI MOSFETs ?
  • Higher current drive  better performance
  • Prophesized to show higher tolerance to scaling.
  • Better integration feasibility, raised source-drain structure, ease in integration.
  • Larger number of parameters to tailor device performance
ibms finfet double gate soi nanoscale device research group
IBMs FinFET / Double-Gate SOI (Nanoscale Device Research Group)

Courtesy: IBM T.J. Watson Research Center, Yorktown Heights, NY

uc berkeley results finfet double gate 2000 04
UC Berkeley Results – FinFET/ Double Gate (2000-04)

Gate Length = 30nm, Oxide thickness =2.1nm

Gate Length = 30nm, Fin Width =20nm

Gate Length = 20nm

intel s trigate soi ssdm 2002
INTEL’s TriGate SOI (SSDM 2002)

Highest ever performance reported for NMOS and PMOS devices on a single substrate !!

intel trigate results 2002 till date
INTEL TriGate Results (2002- till date)

LG = 15nm

LG = 60nm, TSi = 36nm and WSi = 55nm

multi body single gate devices
Multi-Body Single-Gate Devices
  • Multi-Body Single gate devices an attractive option.
  • Increased current drive using a single gate.
  • Total current nearly equals the current thru one body multiplied by the number of body regions.
  • Fabrication feasibility.
  • Feasible for the Dual-Gate, Tri-Gate and -gate devices.

Front-View

Body

GATE

Top-View

device design a brief summary
Device Design (A brief Summary)

Research Initiative

  • Devices under investigation completely novel.
  • Only N-channel devices investigated to some extent.
  • Device structural variations and their effect on performance investigated to a minor degree.
  • Microwave performance of the device’s not investigated at all.

Modeling Approach at U.C. (Semiconductor Devices Laboratory)

  • Numerical device simulators from SILVACO International and ISE.
  • Extensive 3-D modeling of the four N-channel device structures.
  • P-channel devices to be modeled in succession.
  • RF analysis of the N-channel devices followed by the P-channel devices, extraction of important device parameters.
  • Effect of temperature variation on device performance to be analyzed.
multi gate soi mosfets 3 d views
Multi-Gate SOI MOSFETs (3-D Views)

TriGate

Double Gate/

FinFET

-Gate

QuadGate

multi gate soi mosfets 2 d cutplane views
Multi-Gate SOI MOSFETs (2-D Cutplane Views)

Double-gate/

FinFET

TriGate

-Gate

QuadGate

Note: Symmetric and Asymmetric devices possible

the gate transistor the pseudo 4 th gate
The -Gate Transistor (The Pseudo 4th gate)
  • Physics of operation difficult to understand.
  • Lies somewhere in between a Tri-Gate and a Quadruple-gate device as regards structure.
  • Virtual presence of a back-gate in oxide layer that acts as a pseudo-fourth gate.
  • Presence of the virtual gate prevents electric field lines from the drain from penetrating the channel.
  • Amount of vertical gate polysilicon penetration a design factor.

Virtual Back Gate

pigate transistor vertical gate penetration simulation
PiGate Transistor (Vertical Gate Penetration Simulation)

Baseline device dimensions

Gate Length = 50 nm

Body Width = 50 nm

Body Height = 50 nm

Channel Doping = 1x1016 /cm3

Source/ Drain Doping = 1x1019 /cm3

Oxide Thickness = 2 nm

Gate Workfunction = 4.6 eV

  • N-type devices considered.
  • 50-100nm technology node well developed and has translated into a manufacturable technology.
  • Too shallow or too deep an etch in the oxide necessitates accuracy and also poses stringent fabrication tolerances.
  • Optimum value of 50 nm chosen as the vertical polysilicon penetration depth.
drain current i d v ds characteristics
Drain-Current (ID - VDS) Characteristics

FinFET

TriGate

PiGate

QuadGate

gate i d v gs characteristics finfet and trigate
Gate (ID - VGS) Characteristics (FinFET and TriGate)

FinFET Device Characteristics

Threshold Voltage = 0.196 V

Subthreshold Slope = 72 mV/decade

Off Current = 70 A/m

DIBL = 64.67 mV/V

TriGate Device Characteristics

Threshold Voltage = 0.179 V

Subthreshold Slope = 84 mV/decade

Off Current = 37.09 A/m

DIBL = 75.11 mV/V

FinFET

TriGate

Omega-Gate

Quadruple-Gate

gate i d v gs characteristics gate and quadruple gate
Gate (ID - VGS) Characteristics (-gate and Quadruple-gate)

-Gate Device Characteristics

Threshold Voltage = 0.193 V

Subthreshold Slope = 68.08 mV/decade

Off Current = 55.82 A/m

DIBL = 134.9 mV/V

FinFET

TriGate

Omega-Gate

Quadruple-Gate

Quadruple-Gate Device

Characteristics

Threshold Voltage = 0.198 V

Subthreshold Slope = 65 mV/decade

Off Current = 50 A/m

DIBL = 100.74 mV/V

device structural variations gate length
Device Structural Variations (Gate Length)

FinFET

TriGate

-Gate

Quad-Gate

J-T. Park and J-P Colinge, IEEE Transactions on Electron Devices, pp. 2222-2228, vol. 49, no. 12, Dec. 2002.

Device Dimensions

  • Subthreshold Slope = 70-80 mV/decade and lower for switching applications.
  • Number of gates does influence device operation.

Fin Width = 50 nm

Channel Doping = 1x 1016 /cm3

Workfunction = 4.6 eV

Oxide Thickness = 2 nm

A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.

device structural variations channel doping
Device Structural Variations (Channel Doping)

FinFET

TriGate

-Gate

Quad-Gate

J-T. Park and J-P Colinge, IEEE Transactions on Electron Devices, pp. 2222-2228, vol. 49, no. 12, Dec. 2002.

Device Dimensions

  • Near identical behavior in both graphs.
  • Channel doping normally maintained at a low value to minimize effects of scattering.
  • Mobility degradation observed at high values of channel doping.
  • Moderate levels of channel doping could be used.

Fin Height/Width = 50 nm

Gate Length = 50 nm

Workfunction = 4.6 eV

Oxide Thickness = 2 nm

A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.

device structural variations gate length and channel doping
Device Structural Variations (Gate Length and Channel Doping)

FinFET

TriGate

-Gate

Quad-Gate

Device Dimensions

  • Threshold voltage decreases with decrease in gate length, short-channel effect seen to exist in these devices.
  • Threshold voltage sensitive to channel doping beyond 1x1016 /cm3.
  • Can we use channel doping to tailor threshold voltage?

Fin Height = 50 nm

Fin Height = 50 nm

Workfunction = 4.6 eV

Oxide Thickness = 2 nm

A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.

device dimension variations fin height
Device Dimension Variations(Fin Height)

FinFET

TriGate

-Gate

Quad-Gate

Device Dimensions

Gate Length = 50 nm

Channel Doping = 1x1016 /cm3

Workfunction = 4.6 eV

Oxide Thickness = 2 nm

Fin Width = 50 nm

A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.

device dimension variations fin width
Device Dimension Variations(Fin Width)

FinFET

TriGate

-Gate

Quad-Gate

Device Dimensions

Gate Length = 50 nm

Channel Doping = 1x1016 /cm3

Workfunction = 4.6 eV

Oxide Thickness = 2 nm

Fin Height = 50 nm

A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.

device design parameters
Device Design Parameters

FinFET

TriGate

-Gate

Quad-Gate

  • Important step in device design is not patterning of gate region , but instead it is the patterning of the body width.
  • Ideally increase in the number of gates provides an improvement in performance.

Device Dimensions

Workfunction = 4.6 eV

Oxide thickness = 2 nm

device design parameters cont
Device Design Parameters (..cont.)

FinFET

TriGate

-Gate

Quad-Gate

  • TriGate variation minimal when Fin Width is considered.
    • Ideal Gate Length/ Fin Width ratio for FinFET is 1.3 or higher, for a TriGate is unity or higher, for a -gate it is 0.8 or higher and for a Quadruple-gate it is 0.6 or higher.
effect of variation in gate oxide thickness
Effect of Variation in Gate Oxide Thickness

FinFET

TriGate

-Gate

QuadGate

Device Dimensions

Channel Doping = 1x1016 /cm3

Fin Width = 50 nm

Fin Height = 50 nm

Gate Length = 50 nm

Gate Workfunction = 4.6 eV

  • Thinner oxides with higher dielectric constants could be looked upon as an alternative for either device. (Hints at the need to look into new materials (HfO2, ZrO2) as a substitute for SiO2 in nanoscale devices).

A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.

mosfet microwave performance
MOSFET Microwave Performance
  • Silicon-only planar MOSFETs are under consideration.
  • Devices below 200nm gate length are experimental devices.
  • All devices can be optimized for either a larger cut-off frequency or a larger maximum frequency of operation.
  • No strained technology used for MOSFET fabrication.

Juin J. Liou and Frank Schwierz, Solid State Electronics, pp. 1881-1895, vol. 47, 2003.

current gain h 21 unilateral power gain u max
Current Gain (h21) & Unilateral Power Gain (UMax)

Gate Bias = 0.8 Volts

TriGate

FinFET

TriGate

TriGate

FinFET

FinFET

  • Identical behavior for the FinFET and TriGate transistors.
  • TriGate performance again superior to the FinFET.
  • Overall device performance better than that of a planar MOSFET !!

Legend

 Current Gain

 Unilateral Power Gain

A. Breed and K.P. Roenker, IEEE Conference on Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, GA 2001.

variation in the cutoff frequency f t
Variation in the Cutoff Frequency (fT)

Gate Bias = 0.8 Volts

TriGate

TriGate

FinFET

FinFET

  • Similar variation of fT with gate bias and frequency exhibited by the FinFET and TriGate transistors.
  • TriGate exhibits a peak value of 51.5 GHz and the FinFET a peak value of 42.2 GHzfor the cut-off frequency.
  • TriGate is superior again compared to the FinFET (nearly a 20% improvement)!!
  • Values however less than that reported for an optimized planar RF MOSFET transistor (178 GHz - J-J. Liou et. al, Solid State Elec., vol. 47, 1881-1895, 2003).

A. Breed and K.P. Roenker, IEEE Conference on Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, GA 2001.

variation in the maximum frequency of oscillation f max
Variation in the Maximum Frequency of Oscillation (FMax)

Gate Bias = 0.8 Volts

TriGate

TriGate

FinFET

FinFET

  • Similar variation of fMax with gate bias and frequency exhibited by the FinFET and TriGate transistors.
  • TriGate exhibits a peak value of 228 GHz and the FinFET a peak value of 183 GHz.
  • TriGate is superior again compared to the FinFET (20% improvement)!!
  • TriGate performs even better than a planar RF transistor(193 GHz - J-J. Liou et. al, Solid State Elec., vol. 47, 1881-1895, 2003)!!

A. Breed and K.P. Roenker, IEEE Conference on Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, GA 2001.

conclusions and future work
Conclusions and Future Work

Conclusions:

  • Successfully modeled devices in 3-dimensions.
  • Understood device design space and scaling constraints.
  • Undertook a study to understand fabrication tolerances to which every device could be exposed.
  • Both subthreshold and RF performance explored.

Future Work:

  • Model p-channel devices, scaling rules could differ.
  • Understand device design in totality given a variation in two or more than two parameters.
  • Investigate their Microwave characteristics.
  • Comparison with n-channel performance for CMOS and BiCMOS incorporation.
  • Understand effects of temperature on device performance.
references
References
  • A. Breed and K.P. Roenker, “Dual-gate (FinFET) and TriGate MOSFETs: Simulation and design,” Proceedings of the International Semiconductor Device Research Symposium (ISDRS-2003), pp. 150-151, December 2003.
  • J-T. Park and J-P Colinge, “Multiple-Gate SOI MOSFETs: Device Design Guidelines,” IEEE Transactions on Electron Devices, pp. 2222-2228, vol. 49, no. 12, Dec. 2002.
  • Aniket Breed and Kenneth P. Roenker, “A Small-signal, RF Simulation Study of Multiple-gate MOSFET Devices,” IEEE Topical Meeting on Silicon Monolithic ICs in RF Systems, Atlanta, GA, Sept. 2004.