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ELEC7250-001 VLSI Testing Spring 2006

ELEC7250-001 VLSI Testing Spring 2006. Class Project Class Presentation Term Paper. Class Project (25%). Objective: To program a test algorithm and study its applications. Plan: The project will consist of a series of assignments.

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ELEC7250-001 VLSI Testing Spring 2006

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  1. ELEC7250-001 VLSI TestingSpring 2006 Class Project Class Presentation Term Paper ELEC7250-001 Project, Presentation, Paper

  2. Class Project (25%) • Objective: To program a test algorithm and study its applications. • Plan: • The project will consist of a series of assignments. • Initial assignments will be about analyzing the circuit description. These will be common to all students. • In later assignments, each student will work on a separate algorithm and its applications. ELEC7250-001 Project, Presentation, Paper

  3. Project Report • Assignment reports: For each assignment, the work (objective, analysis, algorithms, programs and results) will be recorded in an electronic file and a one-page progress report will be submitted on completion. • Final report: This will contain a complete documentation of the project and will be submitted on completion of the last assignment. • Project evaluation (25%) will be based upon the final report and the timely submission of progress reports. ELEC7250-001 Project, Presentation, Paper

  4. Class Presentation (10%)and Term Paper (10%) • Each student will make a 15-20 minute presentation (April 20, 25 and 27, 2006) to the class describing the project work. • A term paper (about six pages) will contain an in-depth study with references, focused on a specific test algorithm. It should be self-contained. The paper will be due in electronic form (pdf or word) on or before April 13, 2006. ELEC7250-001 Project, Presentation, Paper

  5. Circuit Description • Develop a hierarchical bench format for circuit description. • Bench is a circuit description language used to describe the ISCAS85 and other benchmark circuits. • See http://www.fm.vslib.cz/~kes/asic/iscas/ ELEC7250-001 Project, Presentation, Paper

  6. Example: C17 Circuit # c17 # 5 inputs # 2 outputs # 0 inverter # 6 gates ( 6 NANDs ) INPUT(1) INPUT(2) INPUT(3) INPUT(6) INPUT(7) OUTPUT(22) OUTPUT(23) 10 = NAND(1, 3) 11 = NAND(3, 6) 16 = NAND(2, 11) 19 = NAND(11, 7) 22 = NAND(10, 16) 23 = NAND(16, 19) 22 1 2 3 23 4 5 ELEC7250-001 Project, Presentation, Paper

  7. Project Assignment 1 • Assigned 1/26/06. To be completed 2/2/06. • Develop a hierarchical bench format. • Describe a four-bit ripple-carry adder using the hierarchical bench format. ELEC7250-001 Project, Presentation, Paper

  8. Project Assignment 2 • Assigned 2/2/06. To be completed 2/23/06. • Write a compiler for the hierarchical format: • Compiler is a program with input as the circuit description as hierarchical bench format • Default option • Generate a flat netlist • Generate simulation table • Hierarchical option • Generate simulation tables for all subnetworks in the hierarchical netlist ELEC7250-001 Project, Presentation, Paper

  9. Simulation Table • Contains a gate record for each gate • Gate name • Gate type • Fanin list • Fanout list • Other attributes • Delays • faults ELEC7250-001 Project, Presentation, Paper

  10. Project Assignment 3 (Final) • Assigned 3/9/06. To be completed 4/27/06 • Write a logic simulator for: • Combinational circuits consisting of zero-delay Boolean gates. • Hierarchical bench format netlist input. • Fully specified input vectors and expected responses. • Obtain the following results: • Simulate 4-bit ripple-carry adder with exhaustive set of input vectors and expected outputs, and have your simulator verify the circuit. • Introduce a design error in the netlist and have the simulator list the failing vectors and POs where errors are observed. • Attempt to diagnose the design error. ELEC7250-001 Project, Presentation, Paper

  11. Project Assignment 3 (cont.) • Examine the performance: • Plot CPU time vs. number of vectors for 4-bit adder circuit. • Plot CPU time vs. number of gates for ISCAS’85 circuits each simulated for 1,000 random vectors. • Project report, due 4/27/06: • Describe algorithm implemented. • Provide user information. • Describe the 4-bit adder verification and diagnosis. • Discuss any diagnosis method you have found. • Describe performance. • Class Presentation, schedule on next slide: • Prepare a 20-minute talk on your project including a live demonstration. • Submit powerpoint slides prior to your talk. ELEC7250-001 Project, Presentation, Paper

  12. Class Presentation Schedule ELEC7250-001 Project, Presentation, Paper

  13. Term Paper: Topic Assignment ELEC7250-001 Project, Presentation, Paper

  14. Schedule for Term Paper • Assigned: 3/14/06 • Summary due 3/23/06: • Abstract (200-300 words) • Section titles • List of references • 1-2 pages (hard copy) • Full paper due 4/13/06: • ~ 6 pages (word or pdf) ELEC7250-001 Project, Presentation, Paper

  15. Project Grades A = 25, B = 15, C = 5 ELEC7250-001 Project, Presentation, Paper

  16. ELEC7250 – Spring 2006Final Grade Statistics ELEC7250-001 Project, Presentation, Paper

  17. ELEC7250 – Spring 2006Final Grades ELEC7250-001 Project, Presentation, Paper

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