ee121 john wakerly lecture 4 n.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
EE121 John Wakerly Lecture #4 PowerPoint Presentation
Download Presentation
EE121 John Wakerly Lecture #4

Loading in 2 Seconds...

play fullscreen
1 / 30

EE121 John Wakerly Lecture #4 - PowerPoint PPT Presentation


  • 129 Views
  • Uploaded on

EE121 John Wakerly Lecture #4. Combinational-Circuit Synthesis ABEL. Combinational-Circuit Analysis. Combinational circuits -- outputs depend only on current inputs (not on history). Kinds of combinational analysis: exhaustive (truth table) algebraic (expressions)

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'EE121 John Wakerly Lecture #4' - MikeCarlo


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
ee121 john wakerly lecture 4

EE121 John Wakerly Lecture #4

Combinational-Circuit Synthesis

ABEL

combinational circuit analysis
Combinational-Circuit Analysis
  • Combinational circuits -- outputs depend only on current inputs (not on history).
  • Kinds of combinational analysis:
    • exhaustive (truth table)
    • algebraic (expressions)
    • simulation / test bench
      • Write functional description in HDL
      • Define test conditions / test vectors, including corner cases
      • Compare circuit output with functional description (or known-good realization)
      • Repeat for “random” test vectors
combinational circuit design
Combinational-Circuit Design
  • Sometimes you can write an equation or equations directly using “logic” (the kind in your brain).
  • Example (alarm circuit):
  • Corresponding circuit:
alarm circuit transformation
Alarm-circuit transformation
  • Sum-of-products form
    • Useful for programmable logic devices
  • “Multiply out”:
product of sums form

OR-AND

NOR-NOR

Product-of-sums form

P-of-S preferred in CMOS, TTL (NAND-NAND)

brute force design

row N3 N2 N1 N0 F

0 0 0 0 0 0

1 0 0 0 1 1

2 0 0 1 0 1

3 0 0 1 1 1

4 0 1 0 0 0

5 0 1 0 1 1

6 0 1 1 0 0

7 0 1 1 1 1

8 1 0 0 0 0

9 1 0 0 1 0

10 1 0 1 0 0

11 0 0 1 1 1

12 1 1 0 0 0

13 1 1 0 1 1

14 1 1 1 0 0

15 1 1 1 1 0

Brute-force design
  • Truth table --> canonical sum (sum of minterms)
  • Example:prime-number detector
    • 4-bit input, N3N2N1N0

F = SN3N2N1N0(1,2,3,5,7,11,13)

algebraic simplification
Algebraic simplification
  • Theorem T8,
  • Reduce number of gates and gate inputs
karnaugh map usage
Karnaugh-map usage
  • Plot 1s corresponding to minterms of function.
  • Circle largest possible rectangular sets of 1s.
    • # of 1s in set must be power of 2
    • OK to cross edges
  • Read off product terms, one per circled set.
    • Variable is 1 ==> include variable
    • Variable is 0 ==> include complement of variable
    • Variable is both 0 and 1 ==> variable not included
  • Circled sets and corresponding product terms are called “prime implicants”
  • Minimum number of gates and gate inputs
slide16
When we solved algebraically, we missed one simplification -- the circuit below has three less gate inputs.
yet another example
Yet another example
  • Distinguished 1 cells
  • Essential prime implicants
quine mccluskey algorithm
Quine-McCluskey algorithm
  • This process can be made into a program, using appropriate algorithms and data structures.
    • Guaranteed to find “minimal” solution
  • Required computation has exponential complexity (run time and storage)-- works well for functions with up to 8-12 variables, but quickly blows up for larger problems.
  • Heuristic programs (e.g., Espresso) used for larger problems, usually give minimal results.
lots of possibilities
Lots of possibilities
  • Can follow a “dual” procedure to find minimal products of sums (OR-AND realization)
  • Can modify procedure to handle don’t-care input combinations.
  • Can draw Karnaugh maps with up to six variables.
real world logic design
Real-World Logic Design
  • Lots more than 6 inputs -- can’t use Karnaugh maps
  • Design correctness more important than gate minimization
    • Use “higher-level language” to specify logic operations
  • Use programs to manipulate logic expressions and minimize logic.
  • PALASM, ABEL, CUPL -- developed for PLDs
  • VHDL, Verilog -- developed for ASICs
slide22
ABEL
  • Advanced Boolean Equation Language
    • Developed for use with programmable logic devices, which have a programmable AND-OR structure.
  • Combinational logic functions
    • Operators:
    • Sets:
    • Relations:
    • Intermediate variables

AND, OR, NOT, XOR, XNOR

& # ! $ !$

XBUS = [X3,X2,X1,X0];

XBUS = [1,1,0,1];

XBUS = 13;

(XBUS == YBUS)

(XBUS > [1,1,0,1])

abel language processor compiler
ABEL language processor (compiler)
  • Checks syntax
  • Checks device-pin capabilities
  • Expands language statements and equations
  • Reduces equations into sum-of-products form form for programmable logic device (PLD)
  • Checks test vectors against equations
  • Checks equation requirements (# of inputs, product terms) against PLD resources
  • Determines “fuse map” to program the PLD
nested when statements
Nested WHEN statements
  • Note: different variables can be used in different THEN and ELSE clauses