1 / 28

EE121 John Wakerly Lecture #10

EE121 John Wakerly Lecture #10. Some shift-register stuff Sequential-circuit analysis. Serial data systems (e.g., TPC). Serial data in the phone system (E-1). 2.048 Mb/s links between phone switches and subscribers partitioned into 32 64 Kb/s channels

remy
Download Presentation

EE121 John Wakerly Lecture #10

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. EE121 John Wakerly Lecture #10 Some shift-register stuff Sequential-circuit analysis

  2. Serial data systems (e.g., TPC)

  3. Serial data in the phone system (E-1) • 2.048 Mb/s links between phone switches and subscribers • partitioned into 32 64 Kb/s channels • Each channel gets a timeslot in a “frame” where it can send 8 bits every 125 sec. • 8000 frames/sec

  4. count = 255 Timeslot details

  5. 256 LSBs are bit number Assert shift-registerLOAD input during bit 7 Timeslot number canbe decoded and usedto select source ofparallel data count = 255 Serial data todestination Parallel-to-serial conversion

  6. Synchronize destination’s counter to source’s Detect that acomplete bytehas beenreceived Note: loads 0…0 Holding registerfor completebyte Shift in serial data Serial-to-parallel conversion

  7. Grab complete byte when available Holding-register outputs Serial-in, parallel-outshift register outputs Destination timing

  8. Serial communication on ONE wire • Serial communication requires three signals: CLOCK, SYNC, and DATA. Yet only one “wire” is used. How? • One solution: Manchester code. • Or use a phase-locked loop (analog circuit)to extract clock from the data:

  9. Still a couple of problems • Framing -- SYNC signal • Solution: Use a unique data pattern for SYNC • PLL clock recovery -- what if too many zeroes are transmitted? PLL can’t stay in sync. • Solution: Use a code that guarantees a minimum number of ones • Phone system: Map 00000000 --> 00000010 (creating slight voice distortion) • Gigabit Ethernet: Uses 8B10B code, solving both problems • Map each byte into 8 bits • Use only a “good” subset of 210 code words • Use another code word for synchronization

  10. Shift-register counters • Ring counter

  11. Johnson counter • “Twisted ring” counter

  12. Clocked synchronous seq. circuits • A.k.a. “state machines” • Use edge-triggered flip-flops • All flip-flops are triggered from the same master clock signal, and therefore all change state together • Feedback sequential circuits • No explicit flip-flops; state stored in feedback loops • Example: edge-triggered D flip-flop itself (4 states) • Sections 7.9, 7.10 (advanced courses)

  13. output depends onstate and input typically edge-triggered D flip-flops State-machine structure (Mealy)

  14. output dependson state only typically edge-triggered D flip-flops State-machine structure (Moore)

  15. State-machine structure (pipelined) • Often used in PLD-based state machines. • Outputs taken directly from flip-flops, valid sooner after clock edge. • But the “output logic” must determine output value one clock tick sooner (“pipelined”).

  16. Notation, characteristic equations • Q means “the next value of Q.” • “Excitation” is the input applied to a device that determines the next state. • “Characteristic equation” specifies the next state of a device as a function of its excitation. • S-R latch: Q = S + R´ · Q • Edge-triggered D flip-flop: Q = D

  17. State-machine analysis steps • Assumption: Starting point is a logic diagram. 1. Determine next-state function F and output function G. 2a. Construct state table • For each state/input combination, determine the excitation value. • Using the characteristic equation, determine the corresponding next-state values (trivial with D f-f’s). 2b. Construct output table • For each state/input combination, determine the output value. (Can be combined with state table.) 3. (Optional) Draw state diagram

  18. Example state machine

  19. Excitation equations

  20. Transition equations • Excitation equations • Characteristic equations • Substitute excitation equations into characteristic equations

  21. (output equation) state/outputtable state table transitiontable another name for this function? Transition and state tables (transitionequations)

  22. State diagram • Circles for states • Arrows for transitions (note output info)

  23. Modified state machine • Moore machine MAXS MAXS = Q0  Q1

  24. Updated state/output table, state diagram

  25. Timing diagram for state machine • Not a complete description of machine behavior

  26. Set of registered outputs GOTO or IF Output combinations Can be nested ABEL state diagrams

  27. module SMexample title ’Simple ABEL state_diagram example’ EN pin; Q1, Q0 pin istype ’reg’; MAX, MAXS pin istype ’com’; S = [Q1,Q0]; A = [ 0, 0]; B = [ 0, 1]; C = [ 1, 0]; D = [ 1, 1]; state_diagram S state A: if EN then B else A; state B: if EN then C else B; state C: if EN then D else C; state D: if EN then A else D; equations MAX = (S==D) & EN; MAXS = (S==D); end SMexample ABEL state diagram for example machine

  28. Next time • State-machine design and synthesis

More Related