ece 551 digital system design synthesis l.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
ECE 551: Digital System Design & Synthesis PowerPoint Presentation
Download Presentation
ECE 551: Digital System Design & Synthesis

Loading in 2 Seconds...

play fullscreen
1 / 26

ECE 551: Digital System Design & Synthesis - PowerPoint PPT Presentation


  • 372 Views
  • Uploaded on

ECE 551: Digital System Design & Synthesis . Motivation and Introduction Lectures Set 1 (3 Lectures). Overview. Course Introduction Overview of Contemporary Digital Design Layout Application Specific Integrated Circuit (ASIC) Technologies IC Costs ASIC Design Flows

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'ECE 551: Digital System Design & Synthesis' - LionelDale


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
ece 551 digital system design synthesis

ECE 551: Digital System Design & Synthesis

Motivation and Introduction

Lectures Set 1

(3 Lectures)

overview
Overview
  • Course Introduction
  • Overview of Contemporary Digital Design
    • Layout
    • Application Specific Integrated Circuit (ASIC) Technologies
    • IC Costs
    • ASIC Design Flows
    • The Role of HDLs and Synthesis
  • Summary
course introduction
Course Introduction
  • Purpose:
    • To provide knowledge and experience in performing contemporary logic design based on 1) hardware description languages (HDLs), 2) HDL simulation, 3) automated logic synthesis and 4) timing analysis with consideration for a) pragmatic design and test issues, b) chip layout issues, and c) design reuse in the context of the ASIC (Application Specific Integrated Circuit) and SOC (System-On-a-Chip) technologies.
  • Conduct and Outline
    • Go through the course homepage for 551
    • http://www.cae.wisc.edu/~ece551/spring02/general/conduct.html
layout

Metal 3

Oxide

Metal 2

Metal 1

Transistor

Polysilicon

Diffusion

Substrate

Channel

Layout
  • IC are produced from masks that correspond to geometric layouts produced by the designer or automatically.
  • In CMOS, a typical IC cross-section:
layout continued

Transistor

Channel

Layout (continued)
  • The layout corresponding to the cross-section:
    • The transistor is outlined in broad yellow lines.
    • Everything else is interconnect.
ic implementation technologies
IC Implementation Technologies
  • Implementation technologies are distinguished by:
    • The levels of the layout 1) transistors and 2) interconnect that are:
      • Common to distinct IC designs (L1)
      • Different for distinct IC designs (L2)
    • The use of predesigned layout cells
      • Predesigned cells are used (P1)
      • Predesigned cells are not used (P2)
    • Mechanism used for instantiating distinct IC designs:
      • Metallization (M)
      • Fuses or Antifuses (F)
      • Stored Charge (C)
      • Static Storage (R)
ic implementation technologies continued

STANDARD

IC

ASIC

FULL

CUSTOM

STANDARD

CELL

GATE ARRAY,

SEA OF GATES

FPGA

PLD

IC Implementation Technologies (continued)

SEMI-

CUSTOM

FIELD

PROGRAMMABLE

ic implementation technologies continued8
IC Implementation Technologies (continued)
  • Technologies in terms of Distinguishing Features:
    • Full Custom – P2, M
      • Transistors – L2, Interconnects – L2
    • Standard Cell – P1, M
      • Transistors – L2, Interconnects – L2
    • Gate Array, Sea of Gates – P1, M
      • Transistors – L1, Interconnects – L2
    • FPGA – P1, F or R
      • Transistors – L1, Interconnects – L1
    • PLD – P1, F or C
      • Transistors – L1, Interconnects – L1
ic implementation technologies continued9
IC Implementation Technologies (continued)
  • Technologies in terms of shared fabrication steps (can be used for common transistors/interconnects):
    • Full Custom and Standard Cells – all layers are custom fabricated
    • Gate Arrays and Sea of Gates – only interconnect (metallization) layers custom fabricated
    • FPGAs and PLDs – nothing is custom fabricated
  • Consequences due to economy-of-scale:
    • Fab costs reduced for Gate Arrays and Sea of Gates
    • Fab costs further reduced for FPGAs and PLDs
ic implementation technologies continued10
IC Implementation Technologies (continued)
  • Technologies in terms of layout styles:

Standard Cell

Adjustable Spacing

Megacells

Gate Array - Channeled

Fixed Spacing

Base Cell

ic implementation technologies continued11
IC Implementation Technologies (continued)
  • Technologies in terms of layout styles:

Gate Array - Channel-less

(Sea of Gates)

Base Cell

Gate Array - Structured

Fixed Embedded Block

ic costs
IC Costs
  • An example: 10,000 gate circuit [1]
    • Fixed costs
      • Standard Cell - $146,000
      • Gate Array - $86,000
      • FPGA - $21,800
    • Variable costs
      • Standard Cell - $8 per IC
      • Gate Array - $10 per IC
      • FPGA - $39 per IC
ic costs continued
IC Costs (continued)
  • An example: 10,000 gate circuit
ic costs continued14
IC Costs (continued)
  • Why isn’t FPGA cheaper per unit due to economy-of-scale?
    • The chip area required by each of the successive technologies from Full Custom to FPGAs increases for a fixed-sized design.
    • The larger the chip area, the poorer the yield of working chips during fabrication
    • Also, due to increased sales, FPGA prices have declined since the mid-90’s much faster than the other technologies.
cells
CELLS
  • Can of different sizes, shapes and functions varying from transistors, on-chip resistors to large memory arrays or even a processor (often referred to as IP “intellectual property” core)
  • Typically cells in todays cell libraries are:
    • Gates – AND, OR, NAND, NOR, NOT
    • Complex gates – AOI, OAI
    • Storage elements – Flip-Flops, Lateches
asic cell libraries
ASIC Cell Libraries
  • Sources –
    • ASIC vendor
      • use tools supplied by the vendor, often details are not provided (proprietary)
    • Third party
      • Details are provided, often general enough to be used with a known technology, testing may not be necessary
    • Build your own
      • Complete the layout and test to verify the design and performance, often complex and expensive
asic cell libraries contd
ASIC Cell Libraries (contd.)
  • Cells
    • Transistors and transistors as resisitors
    • Combinational logic cells
      • Gates – number of inputs, performance (drive capability and width)
      • Complex gates
    • Sequential cells
      • Flip-flops, latches
    • Datapath logic cells
      • Multiplexors, adders, ALU, mutipliers
traditional asic design flow

Partition - Data-

path &Control

Draw Datapath

Schematics *

Define System

Architecture

Write

Specifications

Draw Control

Schematics *

Define State

Diag/Tables

Do Physical

Design*

Implement*

Integrate

Design*

Traditional ASIC Design Flow

*Steps followed by validation and refinement

traditional flow problems
Traditional Flow Problems
  • Schematic Diagrams
  • Limited descriptive power
  • Limited portability
  • Limited complexity
  • State Diagrams and Algorithmic State Machines
  • Limited complexity
  • Difficult to describe parallelism
  • Tedious and/or Repetitive Detail
how about hdls instead of diagrams
How about HDLs Instead of Diagrams?
  • HDLs
  • Highly portable (text)
  • Describes multiple levels of abstraction
  • Represents parallelism
  • Provides many descriptive styles
    • Structural
    • Register Transfer Level (RTL)
    • Behavioral
  • Serve as input for synthesis
how about synthesis instead of manual design
How about Synthesis instead of Manual Design?
  • Increased design efficiency
  • Potential for better optimization
  • Ability to explore more of overall design space
  • Reduces verification/validation problem
  • Are there disadvantages?
synthesis design flow

Define Architec-

ture (HDL)*

Write

Specifications

Refine to RTL

(HDL)*

Implement*

Synthesize

RTL*

Physical

Design*

Partition Arch-

itecture

Synthesis Design Flow

*Steps followed by validation and refinement

contemporary design flow

Define Architec-

ture (HDL)*

Preliminary

Physical Design

Write

Specifications

Implement*

Synthesize

RTL*

Refine to

RTL*

Physical

Design*

Select IP

Cores

Partition Arch-

itecture

Contemporary Design Flow

*Steps followed by validation and refinement

newer technologies and design flows
Newer technologies and design flows
  • System on Chip (SOC)
    • Designers are provided with IP cores
    • The main function is to glue many cores and generate/design only those components for which cores and designs may not be available
    • Used in ASIC as well as custom design environment
    • The issues relevant to this will be discussed near the end of the course
summary
Summary
  • Course Conduct – Be familiar with it
  • Application Specific Integrated Circuit (ASIC) Technologies – provides a basis for understanding what we are designing
  • IC Costs – Gives a basis for technology selection
  • ASIC Design Flows
    • The role of HDLs and synthesis
    • Provides a structure for what we are to learn
references
References
  • Smith, Michael J. S., Application-Specific Integrated Circuits, Addison-Wesley, 1997.
  • For layout refer to texts for ECE 555 and ECE 755