ECE U322 Digital Logic Design

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## ECE U322 Digital Logic Design

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**ECE U322Digital Logic Design**• Lectures 14: • Binary Adders • Binary Decoder • Reading: Marcovitz 5.2 5.3 • Midterm Exam on Thursday next week, October 13! Oct. 6 2005**Half Adder**• Combinational circuit the performs the addition of two bits. Full Adder • Combination circuit that performs the addition of three bits (two bits and a carry in). 2**Binary Ripple Carry Adder**• The full adders are connected in cascade, with the carry output from one full adder connected to the carry input of the next-higher-order full adder. 3**How to build a binary subtractor**• (A - B) = A + (2’s complement of B) • Invert B inputs • Add 1 to A - B • Can set carry in to 1 to accomplish this 4**Binary subtractor**• Binary subtractor using full adders: • S = A – B =A +(2’complement of B) 5**Binary Adder/Subtractor**• Binary Adder and Binary Subtractor are very similar • Don’t build two separate units -- build one adder/subtractor • S input tells me if I want to subtract • S = 0 Add A + B • S = 1 Subtract: 6**Signed numbers**• Overflow cannot occur for addition when one number is positive and the other is negative. • Overflow may occur only when adding numbers that are both positive or both negative. • overflow if adding two posititve numbers and result is negative, or • adding two negative numbers and result is positive 9**Carry out and Overflow**• 5, 7, -5, -7 represented as 4 bit, signed values: • 0101 0111, 1011, 1001 5 + 7 0101 0111 __overflow, __ carry out 10**Overflow and Carryout**5 -7 1 0101 1001 1110 __overflow, __ carryout 11**Carry out and overflow**- 5 + 7 111 1011 0111 10010 ___overflow, __carry out 12**Overflow and Carry Out**-5 -7 11 1011 1001 10100 __overflow, __ carry out 13**A(N-1)**B(N-1) A(1) B(1) A(0) B(0) C(n) C(1) C(0) Signal from one bit block to the next is carryout for that block. An n-bit adder Generalize the four bit adder to n bits: 14**Carry Lookahead Adder**• Slowest part of ripple carry adder is computation of last carry • want to speed this up • Reduced delay at the price of more complex hardware: area, speed tradeoff • Redesign the carry logic so that it is two-levels of logic: • more complex than ripple carry chain • faster 16**Carry-lookahead adder**• First compute carry propagate, generate: • Pi = ai xor bi • Gi = ai bi • Compute sum and carry from P and G: • si = ai xor bi xorci = Pi xor ci • ci+1 = Gi + Pici 17**Carry-lookahead adder**• ci+1 = Gi + Pici c1 = G0 + P0c0 c2 = G1 + P1c1 = c3 = G2 + P2c2 = c4 = G3 + P3c3 = 18**Carry-lookahead expansion**• Can recursively expand carry formula: • ci+1 = Gi + Pi(Gi-1 + Pi-1ci-1) • ci+1 = Gi + PiGi-1 + PiPi-1 (Gi-2 + Pi-1ci-2) • Expanded formula does not depend on intermediate carries. • Allows carry for each bit to be computed independently. 19**A0**A1 Decoders • n-bits represent 2n different combinations: 22**Binary**Decoder n inputs 2n outputs Binary Decoder • Logic with n input lines and 2n output lines. • Only one output is a 1 for any given input. 23**X**Y F F F F 0 1 2 3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 F0 = X'Y' F1 = X'Y F2 = XY' F3 = XY X Y • truth table for 2 to 4 decoder: • Note: Each output is a 2-variable minterm (X'Y', X'Y, XY' or XY) 24**n-bit**code n to 2n decoder up to 2n output lines : : Decoders • In general, for an n-bit code, a decoder could select up to 2n lines: 28**Decoder Expansion**• When a certain size of decoder is needed, but only smaller sizes are available. • It is possible to combine two or more decoders in a hierarchy. 29**Combinational Circuit Implementation**• Decoders can implement any combinational circuit with n inputs and m outputs using a _____________ decoder and ________ gates. 30**Example: Implement a Binary Adder using a decoder.**• Express as sum of minterms. S(X,Y,Z) = S m( ) C(X,Y,Z) = S m( ) 31**Choose a decoder that implements all the minterms of the**input variables. • Select inputs to each OR gate based on the list of minterms of each function. 32**Example:**33**Encoder**• 2n (or fewer) input lines and n output lines. • The output lines generate the binary code corresponding to the input value, assuming only one input is high. • An encoder is the reverse function of a decoder 34**8-to-3-line Encoder**8-to-3 Encoder 35**Example: Octal-to-Binary Encoder**A0 = A1 = A2 =**Ambiguity**• If two inputs are active simultaneously, the output produces an incorrect combination. • To resolve, some encoders use an input priority to ensure that only one input is encoded. • An output of all 0’s is generated when all the inputs are 0. This is the same as when D0 is equal to 1. • This discrepancy can be resolved by providing one more output to indicate that at least one input is equal to 1. This is called the VALID output. 37**Priority Encoder**• If two or more inputs are equal to 1 at the same time, the input with highest priority takes precedence. 38**Example:**Truth Table of 4-Input Priority Encoder 39**Multiplexers**42**Multiplexers (MUX)**• Data selector. • Selects binary information from one of many input lines to a single output line. • Selection inputs control which particular input line to select. • Normally, there are 2n input lines, n selection inputs, and one output. 43**I0**I0 I1 I1 Y Y I2 I2 I3 I3 0 1 2 3 2-to-4 Decoder S1 S0 S1 S0 Multiplexer Four-to-one multiplexer contains a decoder. 45**Multiplexer**• An application: Helps share a single communication line among a number of devices. At any time, only one source and one destination can use the communication line. 46**Outputs**Y0 = D.S1'.S0' Y1 = D.S1'.S0 Data D demux Y2 = D.S1.S0' Y3 = D.S1.S0 S1 S0 select Demultiplexer • Given an input line & a set of selection lines, the demultiplexer will direct data from input to a selected output line. • An example of a 1-to-4 demultiplexer: 47**Y0 = D.S1'.S0'**2x4 Decoder S1 S0 Y1 = D.S1'.S0 Y2 = D.S1.S0' E Y3 = D.S1.S0 D Demultiplexer • The demultiplexer is actually identical to a decoder with enable, as illustrated below: 48