3-6 Encoders

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## 3-6 Encoders

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**3-6 Encoders**Encoders Performs the inverse operation of a decoder 2n inputs =>n outputs (binary code) Table 3-5 (Truth Table for octal-to-binary encoder) A0 = D1 + D3 + D5 + D7 A1 = D2 + D3 + D6 + D7 A2 = D4 + D5 + D6 + D7**Ambiguity in octal-to-binary encoder**• Two inputs are active simultaneously, the outputs produces an incorrect combination. • When the inputs are 00000000, 00000001 output is same(0) • Priority Encoder • implements a priority**3-7 Multiplexers (MUX)**• Select binary information from one of many input lines (2n) and directs the information to a single output line. • Selection inputs (n) • Fig.3-19 (4-to-1-Line Multiplexer)**Constructed with transmission gates**• Fig.3-20 (4-to-1-Line Multiplexer with transmission gates)**3-7 Multiplexers**• Combinational Circuit Implementation • Decoder + OR gates • Fig. 3-22 • F(X, Y, Z) = m(1, 2, 6, 7) • X S1, Y S2 • input of multiplexers : (by truth table) • 0 : ground signal, 1 : power signal(+VDD or +VCC)**Fig. 3-23**• F(A,B,C,D) = m(1, 3, 4, 11, 12, 13, 14, 15)**Demultiplexer**• Performs the inverse of the multiplexing operation • Fig. 3-24(1 -to- 4-Line demultiplexer) • identical to 2-to-4-line decoder with enable input.