ABLE

1. T ABLE D.4 ( Continued ) Mnemonic Size Operands Operation CC flags (Name) performed affected dst src S Z O C HL T Halts execution un til (Halt) reset or external in terrupt o ccurs IDIV B,D reg for B: ? ? ? ? (Signed mem [AL]/[src];  divide) AL quotient;  AH remainder for D: [EAX]/[src];  EAX quotient;  ED X remainder IMUL B,D reg (double-length product) ? ? x x (Signed mem for B:   m ultiplication) AX [AL] [src] for D:  ED X,EAX [EAX]  [src] D reg reg (single-length pro duct) ? ? x x   reg mem reg [reg] [src]  IN B,D dst = AL AL or EAX [src] (Isolated or EAX input) src = imm8 or [D X]  INC B,D reg dst [dst] + 1 x x x (Increment ) mem INT D imm8 Push EFLA GS; (Software Push EIP;  in terrupt) EIP address (determined b y imm8) Table D.4 – page 3

2. T ABLE D.4 ( Continued) Mnemonic Size Operands Operation CC flags (Name) performed affected dst src S Z O C IRET D P op EIP; x x x x (Return from P op EFLA GS in terrupt)  LEA D reg mem reg EA of src (Load effectiv e address)  – LOOP D target ECX [ECX] 1;  (Lo op) If ( [ECX] 0 )  EIP target  – LOOPE D target ECX [ECX] 1;  (Lo op on If ( [ECX] 0 ^ equal/zero) [Z] = 1 )  EIP target  – LOOPNE D target ECX [ECX] 1;  (Lo op on If ( [ECX] 0 ^  not equal/ [Z] 1 )  not zero) EIP target  MO V B,D reg reg dst [src] (Mo v e) reg mem mem reg reg imm mem imm  MO VSX B reg reg reg sign extend [src] (Sign extend reg mem b yte in to register) Table D.4 – page 4

3. T ABLE D.4 ( Continued) Mnemonic Size Operands Operation CC flags (Name) performed affected dst src S Z O C  MO VZX B reg reg reg zero extend [src] (Zero extend reg mem b yte in to register) MUL B,D reg (double-length pro duct) ? ? x x (Unsigned mem for B:   m ultiplication) AX [AL] [src] for D:  ED X,EAX [EAX]  [src]  NEG B,D reg dst 2's-complement x x x x (Negate) mem [dst] NOP alias for: (No op eration) X CHG EAX,EAX  NOT B,D reg dst [dst ] (Logical mem complement)   OR B,D reg reg dst [dst] [src] x x 0 0 (Logical OR) reg mem mem reg reg imm mem imm  OUT B,D dst = imm8 dst [AL] or [EAX] (Isolated or [D X] output) src = AL or EAX Table D.4 – page 5

4. T ABLE D.4 ( Continued) Mnemonic Size Operands Operation CC flags (Name) performed affected dst src S Z O C  POP D reg dst [[ESP]];  (Pop off mem ESP [ESP] + 4 stack) POPAD D Pop eight doublewords (Pop off off stack in to stack in to EDI, ESI, EBP , discard, all registers EBX, EDX, ECX, EAX;  except ESP) ESP [ESP] + 32  – PUSH D reg ESP [ESP] 4;  (Push on to mem [ESP] [src] stac k) imm PUSHAD D Push contents of (Push all EAX, ECX, EDX, EBX, registers ESP , EBP , ESI, EDI on to stack) on to stack;  – ESP [ESP] 32 R CL B,D reg imm8 See Figure 2.32 b ; ? x (Rotate left reg CL src operand is with C flag) mem imm8 rotation count mem CL R CR B,D reg imm8 See Figure 2.32 d ; ? x (Rotate righ t reg CL src operand is with C flag) mem imm8 rotation count mem CL  RET EIP [[ESP]];  (Return from ESP [ESP] + 4 subroutine) Table D.4 – page 6

5. T ABLE D.4 (Continued) Mnemonic Size Operands Operation CC flags (Name) performed affected dst src S Z O C R OL B,D reg imm8 See Figure 2.32 a ; ? x (Rotate left) reg CL src operand is mem imm8 rotation count mem CL R OR B,D reg imm8 See Figure 2.32 c ; ? x (Rotate righ t) reg CL src operand is mem imm8 rotation count mem CL SAL B,D reg imm8 See Figure 2.30 a ; x x ? x (Shift reg CL src operand is arithmetic mem imm8 shift count left) mem CL same as SHL SAR B,D reg imm8 See Figure 2.30 c ; x x ? x (Shift reg CL src operand is arithmetic mem imm8 shift count right) mem CL  – SBB B,D reg reg dst [dst] [src] x x x x – (Subtract reg mem [CF] with b orrow) mem reg reg imm mem imm SHL B,D reg imm8 See Figure 2.30 a ; x x ? x (Shift reg CL src operand is left) mem imm8 shift count same as SAL mem CL Table D.4 – page 7

6. T ABLE D.4 (Continued) Mnemonic Size Operands Operation CC flags (Name) performed affected dst src S Z O C SHR B,D reg imm8 See Figure 2.30 b ; x x ? x (Shift reg CL src operand is righ t) mem imm8 shift coun t mem CL  STC CF 1 1 (Set carry flag)  STI IF 1 (Set in terrupt flag)  – SUB B,D reg reg dst [dst] [src] x x x x (Subtract) reg mem mem reg reg imm mem imm TEST B,D reg reg [dst] ^ [src]; x x 0 0 (T est) mem reg set flags based reg imm on result mem imm X CHG B,D reg reg [reg]  [src] (Exchange) reg mem   X OR B,D reg reg dst [dst] [src] x x 0 0 (Exclusive reg mem OR) mem reg reg imm mem imm Table D.4 – page 8

7. T ABLE D.5 IA-32 conditional jump instructions Mnemonic Condition Condition code name test JS Sign (negative) SF = 1 JNS No sign (positive or zero) SF = 0 JE/JZ Equal/Zero ZF = 1 JNE/JNZ Not equal/Not zero ZF = 0 JO Overflow OF = 1 JNO No overflow OF = 0 JC/JB Carry/Unsigned below CF = 1 JNC/JAE No carry/Unsigned above or equal CF = 0  JA Unsigned above CF ZF = 0  JBE Unsigned below or equal CF ZF = 1  JGE Signed greater than or equal SF OF = 0  JL Signed less than SF OF = 1   JG Signed greater than ZF (SF OF) = 0   JLE Signed less than or equal ZF (SF OF) = 1