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ECE 545 - Lecture 13. Motorola 68HC11. Resources. 68HC11 E-series Reference Guide and if necessary 68HC11 E-series Technical Data 68HC11 Reference Manual all available at http://www.technologicalarts.com/myfiles/links.html Optionally: Peter Spasov, Microcontroller Technology ,

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ECE 545 - Lecture 13

Motorola 68HC11


Resources

  • 68HC11 E-series Reference Guide

  • and if necessary

    • 68HC11 E-series Technical Data

    • 68HC11 Reference Manual

  • all available at

  • http://www.technologicalarts.com/myfiles/links.html

  • Optionally:

  • Peter Spasov, Microcontroller Technology,

  • any edition, Prentice-Hall, Chapter 2, Software,

  • and Chapter 7 Clocked Operation

  • (you can borrow this book from the ECE 447 students).


Basic Computer System

Parallel

I/O Device

Serial

I/O Device

Parallel

Data

Serial

Data

Memory

Program

+ Data

I/O Interface

CPU

Data Bus

Address Bus

Control Bus


Microprocessor - usually memory off-chip and only basic

I/O interface on chip

e.g., Intel 8008, 8080, 8086, 80286, Pentium

Single-chip microcomputer - CPU, memory, I/O interface,

and simple I/O devices on one LSI chip

e.g., Intel 8048, 8051, Motorola 68HC11, 68HC16


Microcontroller: I/O oriented single-chip microcomputer

Microcontroler vs. other single-chip microcomputers:

  • Extended I/O capabilities

synchronous and asynchronous communication devices,

A/D and D/A converters, timers, counters, watchdogs

  • Interrupt handling

increased ability to prioritize levels of interrupts and mask

individual interrupts

  • Instruction set

instructions oriented toward bit manipulation,

operations on single bits of memory words or I/O ports


Early microcroprocessors

(8080, 6800, Z80)

integration

performance

General-purpose

microprocessors

Single-chip

microcomputers

(e.g., Pentium, Alpha, Power PC)

(e.g., MC68HC11, 8051)

- small price

- low power consumption

- built-in memory

- built-in I/O devices

- high speed

- long word size

volume

sold

x 1

x 10



Organization of MC68HC11 in the Single-Chip Mode

RAM

CPU

ROM

EEPROM

A/D

SPI

TIMER

SCI

8 (4)

8

4

2

PORT A

PORT B

PORT C

PORT D

PORT E

3

3

2

8

8

6

8 (4)


Organization of MC68HC11

in the Expanded Bus Mode

RAM

CPU

ROM

EEPROM

A/D

SPI

TIMER

SCI

8 (4)

8

4

2

PORT D

PORT E

PORT A

6

8 (4)

3

3

2

EXTERNAL RAM

EXTERNAL EPROM

EXTERNAL I/O

EXTERNAL ROM


Abbreviations

CPU - Central Processing Unit

:= ALU (Arithmetic Logic Unit) + Control

RAM - Random Access Memory := Read/Write Memory

ROM - Read Only Memory (non-volatile)

EPROM - Erasable Programmable ROM

EEPROM - Electrically Erasable ROM

SCI - Serial Communication Interface

(asynchronous serial communication interface)

SPI - Serial Peripheral Interface

(synchronous serial communication interface)

A/D - analog-to-digital converter



Register structure of MC6811

Accumulators A and B or

A

B

7

0

7

0

D

Double Accumulator D

0

15

X-index register

IX

0

15

Y-index register

IY

0

15

Stack Pointer

SP

0

15

Program Counter

PC

0

15

Condition Code Register

CCR

7

0

S X H I N Z V C


Condition Code Register

CCR

7

0

S X H I N Z V C

carry / borrow

overflow

zero

negative

I-interrupt mask

half-carry (from bit 3)

X-interrupt mask

stop disable



Input/Output Ports

Input

Pins

Output

Pins

Bidirectional

Pins

Shared

Functions

Port

Port A

Port B

Port C

Port D

Port E

3

8

3

8

2

8

6

Timer

High Order Address

Low Order Address

and Data Bus

SCI and SPI

A/D Converter


Memory mapped I/O

Separate I/O

(e.g., Intel)

(e.g., Motorola)

0

0

0

I/O

max

I/O

MAX

MAX

Control lines:

read/write

Control lines:

read/write

memory/io


Memory map of MC68HC11E1

$0000-$01FF

512 bytes RAM

$0000

$0000

EXT

$1000

$1000

$1000-$103F

64 bytes I/O registers

EXT

$B600

$B600

$B600-$B7FF

512 bytes EEPROM

EXT

$FFFF

$FFFF

Single-chip mode

Expanded bus mode


I/O Device Architecture

I/O device

Control registers

instructions

address1/name1

…..

Status registers

status of the device

…..

. . . . .

Data registers

inputs (operands)

…..

addressN/nameN

outputs (results)


Input/Output Register Types

1. Control registers - hold instructions that regulate the operation of

internal I/O devices

2. Status registers - indicate the current status of internal I/O devices

3. Data registers - hold the input data sent to the I/O device and output

data generated by this device

4. Data direction registers - control the direction (in or out) of the data

flow to/from bidirectional data registers


Assembly Language

vs.

Machine Code


Assembly language vs. machine code

Assembly language

[label] mnemonic [operands]

START CLRA

LDAA #$4A

LDAA $5B, Y

Machine code

[prebyte] opcode [operands]

$4F

$86 $4A

$18 $A6 $5B


Machine code

Number of instructions represented using

a single-byte opcode

236

Number of instructions represented using

a combination prebyte+opcode

76

Values of prebytes

18, 1A, CD


; move.s11

; function that transfer an array of 128 bytes

; starting at location $C800 to the memory area

; starting at location $D800

SECTION .text

transfer:

LDX #$C800

LDY #$D800

loop_begin

LDD 0,X

STD 0,Y

INX

INX

INY

INY

CPX #$C880

BNE loop_begin

RTS

END

move.s11


move.lst

C:/introl/Examples/E Sep 24 00:41 19102 Page 1

1 ; move.s11

2 ; function that transfer an array of 128 bytes

3 ; starting at location $C800 to the memory area

4 ; starting at location $D800

5

6 SECTION .text

7

8 00000000 transfer:

9 00000000 cec800 LDX #$C800

10 00000003 18ced800 LDY #$D800

11 00000007 loop_begin

12 00000007 ec00 LDD 0,X

13 00000009 18ed00 STD 0,Y

14 0000000c 08 INX

15 0000000d 08 INX

16 0000000e 1808 INY

17 00000010 1808 INY

18 00000012 8cc880 CPX #$C880

19 00000015 26f0 BNE loop_begin

20 00000017 39 RTS

21

22 END


C:/introl/Examples/E Sep 24 00:41 19102 Page 2

Section synopsis

1 00000018 ( 24) .text

C:/introl/Examples/E Sep 24 00:41 19102 Page 3

Symbol table

.text 1 00000000 | loop_begin 1 00000007 | transfer E 1 00000000

C:/introl/Examples/E Sep 24 00:41 19102 Page 4

Symbol cross-reference

.text *6

loop_begin *11 19

transfer *8


Groups of Instructions Sep 24 00:41 19102 Page 2


Groups of instructions (1) Sep 24 00:41 19102 Page 2

1. Data handling instructions

a. Move instructions

(e.g., load, store, exchange)

b. Alter data instructions

(e.g., clear, increment, decrement)

c. Edit instructions

(e.g., shift, rotate)

2. Arithmetic instructions

(e.g., add, subtract, multiply, divide, negate)

3. Logic instructions

(e.g., and, or, xor)

4. Data test instructions

(e.g. compare, test, bit test)


Groups of instructions (2) Sep 24 00:41 19102 Page 2

5. Control instructions

(e.g., jump, branch)

6. Condition code instructions

(e.g., set carry, clear overflow flag)

7. Stack operations

(e.g. push, pull)

8. Subroutine-related instructions

(e.g. jump to subroutine, return from subroutine)

9. Interrupt-related instructions

(e.g. software interrupt, return from interrupt)


Addressing Modes Sep 24 00:41 19102 Page 2


Move instructions (1) Sep 24 00:41 19102 Page 2

N Z V C

1. memory  register

LDA [A, B]

LD [D, X, Y, S]

2. register  memory

STA [A, B]

ST [D, X, Y, S]

3. register  register

TAB, TBA

4. memory  memory

IMM, DIR, EXT, IND

0 –

0 –

DIR, EXT, IND

0 –

INH


Move instructions (2) Sep 24 00:41 19102 Page 2

N Z V C

1. register  register

XGD [X, Y]

– – – –

INH


Addressing modes of the LDAA instruction Sep 24 00:41 19102 Page 2

Immediate mode

$5C  A

LDAA #$5C

Direct mode

($001B)  A

LDAA $1B

Extended mode

($6D00)  A

LDAA $6D00

Indexed mode

(IX+$56)  A

LDAA $56, X

LDAA $56, Y

(IY+$56)  A


Instruction Table Sep 24 00:41 19102 Page 2


Addressing modes of MC68HC11 (1) Sep 24 00:41 19102 Page 2

1. Inherent: Opcode contains reference.

2. Immediate: Data follows opcode.

3. “Direct”: Base page, Page 0;

Low byte of address follows opcode.

High byte of address set to zero.

4. Extended: Direct;

Complete address of the operand

follows the opcode.


Addressing modes of MC68HC11 (2) Sep 24 00:41 19102 Page 2

5. Indexed Contents of X or Y index register

added to the unsigned offset in the

byte following the opcode to form

effective address

6. Relativesigned byte following the opcode

added to the pre-incremented

program counter PC to form effective

address


Arithmetic Instructions Sep 24 00:41 19102 Page 2


Arithmetic instructions (1) Sep 24 00:41 19102 Page 2

N Z V C

1. addition Acc + M  Acc

ADD [A, B, D]

ADC [A, B]

2. subtraction Acc – M  Acc

SUB [A, B, D]

SBC [A, B]

IMM, DIR, EXT, IND

IMM, DIR, EXT, IND

3. negation -X

NEG [A, B]

NEG

INH

EXT, IND


Unsigned vs. signed numbers Sep 24 00:41 19102 Page 2

B = b7 b6 b5 b4 b3 b2 b1 b0

Unsigned number

weights

128 64 32 16 8 4 2 1

B = b7 b6 b5 b4 b3 b2 b1 b0

7

B = b020 + b121 + b222 + b323 + b424 + b525 + b626 + b727 =

bi2i

i=0

Signed number

weights

-128 64 32 16 8 4 2 1

B = b7 b6 b5 b4 b3 b2 b1 b0

6

bi2i

B = b020 + b121 + b222 + b323 + b424 + b525 + b626 - b727 = - b727 +

i=0


Definition of the Condition Code Register flags (1) Sep 24 00:41 19102 Page 2

Zero flag - Z

zero result

Z = 1 if result = 0

0 otherwise

Negative flag- N

negative result

N = sign bit of the result

r7 - for 8-bit operands

r15 - for 16-bit operands


Definition of the Condition Code Register flags (2) Sep 24 00:41 19102 Page 2

Carry flag - C

out-of-range for unsigned numbers

C = 1 if result > MAX_UNSIGNED or

result < 0

0 otherwise

where MAX_UNSIGNED = 28-1 for 8-bit operands (registers A, B)

216-1 for 16-bit operands (register D)

Overflow flag - V

out-of-range for signed numbers

V = 1 if result > MAX_SIGNED or

result < MIN_SIGNED

0 otherwise

where MAX_SIGNED = 27-1 for 8-bit operands (registers A, B)

215-1 for 16-bit operands (register D)

MIN_SIGNED = -27 for 8-bit operands (registers A, B)

-215 for 16-bit operands (register D)


Overflow for signed numbers (1) Sep 24 00:41 19102 Page 2

Indication of overflow

Negative

+ Negative

= Positive

Positive

+ Positive

= Negative

Formulas

Overflow2’s complement = xk-1 yk-1 sk-1 + xk-1 yk-1 sk-1 =

= ck ck-1


Overflow for signed numbers (2) Sep 24 00:41 19102 Page 2

xk-1 yk-1 ck-1 ck sk-1 overflow ckck-1

0

1

0

1

0

1

0

1

0

0

1

1

0

0

1

1

0

1

0

0

0

0

1

0

0

0

0

0

1

1

1

1

0

0

0

1

0

1

1

1

0

1

1

0

1

0

0

1

0

1

0

0

0

0

1

0


Condition code instructions Sep 24 00:41 19102 Page 2

1. set a flag 1  flag

SE [C, V, I]

2. clear a flag 0  flag

CL [C, V, I]

3. change all flags A  CC

TAP

4. read all flags CC  A

TPA


Arithmetic instructions (2) Sep 24 00:41 19102 Page 2

N Z V C

1. addition Reg + B  Reg

ABA

AB [X, Y]

2. subtraction A – B  A

SBA

INH

– – – –

INH


Arithmetic instructions (3) Sep 24 00:41 19102 Page 2

N Z V C

1. unsigned multiplication A x B  D

MUL

2. unsigned division D/IX  IX D mod IX  D

IDIV

3. unsigned fractional division D < IX

216 D/ IX  IX

216 D mod IX  D

4. decimal adjustment

DAA

– – –

INH

– 0

INH

FDIV

INH

?

INH


Extending the number of bits of a signed number Sep 24 00:41 19102 Page 2

xk-1xk-2 … x1x0

X

yk’-1yk’-2 … ykyk-1yk-2 … y1y0

Y

two’s complement

xk-1 xk-1 xk-1 . . .xk-1xk-2 … x1x0


Other Instructions Sep 24 00:41 19102 Page 2


Alter data instructions Sep 24 00:41 19102 Page 2

N Z V C

1. 0  register

CLR [A, B]

2. 0  memory

CLR

0 1 0 0

INH

0 1 0 0

EXT, IND

3. increment X++

INC [A, B]

INC

IN [X, Y]

4. decrement X--

DEC [A, B]

DEC

DE [X, Y]

INH

EXT, IND

INH

– – –

INH

EXT, IND

INH

– – –


Edit instructions - Shifts Sep 24 00:41 19102 Page 2

N Z V C

. . .

1. logical shift right

LSR [A, B, D]

LSR

2. arithmetic shift right

ASR [A, B, D]

ASR

3. arithmetic/logical shift left

ASL [A, B, D], LSL [A, B, D]

ASL, LSL

0

C

0

n-1

INH

EXT, IND

0

. . .

C

0

n-1

INH

EXT, IND

. . .

C

0

0

n-1

INH

EXT, IND


Edit instructions - Rotations Sep 24 00:41 19102 Page 2

N Z V C

. . .

1. rotation right

ROL [A, B]

ROL

2. rotation left

ROR [A, B]

ROR

0

7

C

INH

EXT, IND

. . .

0

7

0

C

INH

EXT, IND


Logic instructions (1) Sep 24 00:41 19102 Page 2

N Z V C

1. AND Acc & M  Acc

AND [A, B]

2. OR Acc | M  Acc

ORA [A, B]

3. XOR Acc  M  Acc

EOR [A, B]

0 –

IMM, DIR, EXT, IND

0 –

IMM, DIR, EXT, IND

0 –

IMM, DIR, EXT, IND


Logic instructions (2) Sep 24 00:41 19102 Page 2

N Z V C

1. complement X  X

COM [A, B]

COM

2. bit set M | mask  M

BSET

3. bit clear M & mask  M

BCLR

INH

EXT, IND

0 1

DIR, IND

0 –

DIR, IND

0 –


Data test instructions (1) Sep 24 00:41 19102 Page 2

N Z V C

1. comparison R - M

CMP [A, B]

CP [D, X, Y]

IMM, DIR, EXT, IND

2. comparison A – B

CBA

INH

3. test register

TST [A, B]

4. test memory

TST

0 0

INH

0 0

EXT, IND


Data test instructions (2) Sep 24 00:41 19102 Page 2

N Z V C

1. Bit test Acc & memory

BIT [A, B]

IMM, DIR, EXT, IND

0 –


Control instructions (1) - Branches Sep 24 00:41 19102 Page 2

N Z V C

– – – –

REL

after comparison register vs. memory

unsigned numbers

signed numbers

BHI higher >

BLO lower <

BHS higher or same 

BLS lower or same 

BGT greater than >

BLT less than <

BGE greater than or equal 

BLE less than or equal 

BEQ equal =

BNE not equal 


Control instructions (2) - Branches Sep 24 00:41 19102 Page 2

after arithmetic operations (testing for overflow)

unsigned numbers

signed numbers

BCS carry set

BCC carry clear

BVS overflow set

BVC overflow clear

after testing register or memory

BPL plus  0

BMI minus < 0

unconditional

BRA always

BRN never


Condition code instructions Sep 24 00:41 19102 Page 2

1. set a flag 1  flag

SE [C, V, I]

2. clear a flag 0  flag

CL [C, V, I]

3. change all flags A  CC

TAP

4. read all flags CC  A

TPA


Data test instructions (1) Sep 24 00:41 19102 Page 2

N Z V C

1. comparison R - M

CMP [A, B]

CP [D, X, Y]

IMM, DIR, EXT, IND

2. comparison A – B

CBA

INH

3. test register

TST [A, B]

4. test memory

TST

0 0

INH

0 0

EXT, IND


Data test instructions (2) Sep 24 00:41 19102 Page 2

N Z V C

1. Bit test Acc & memory

BIT [A, B]

IMM, DIR, EXT, IND

0 –


Opcode Map Sep 24 00:41 19102 Page 2


Interface to External Memory Sep 24 00:41 19102 Page 2


Write Cycle Sep 24 00:41 19102 Page 2


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