Chinese Real Time VLBI Correlator

Chinese Real Time VLBI Correlator Xiang Ying, Xu Zhijun, Zhu Renjie, Zhang Xiuzhong, Shu Fengchun, Zheng Weimin Shanghai Astronomical Observatory China 5th International e-VLBI Workshop 17-20 September 2006

OUTLINE • Main Characteristics • Architecture of the Correlator • Clock Module • PBI(Playback Interface) Module • FFT & MAC(Multiply and Accumulate Card) Module • MCC(Master Control Card) Module • Some results • Future Plan

Main Characteristics • 5 Stations FX Correlator ( 5 stations, 8 IFs ) • Maximum data rate：256Mbps (8 channels) • Integration Time：32.768 millisecond – 1 hour (typical 1s) • Input data format: MKIV, MKV or others( VSI in plan) • data source ：Disk Array, Network • Output: via net and disk files ( FITS format in plan) • Fringe searcher, Phase Cal

Architecture of Correlator

FFT & MAC (xc4vsx35) MCC (xc4vFX20) CCC+LTA MOXA Card PBD PBI (xc2v3000)

Clock Board In the FFT & MAC & MCC Chassis: • Provide 32MHz clock to pbi module (5 stations) • Provide 32MHz clock to FFT+MAC module (8 channels) • Provide 32MHz clock to MCC • Provide 32MHz clock to LTA

PBI 1. Input buffer 2. NRZM(Non Return to Zero Mark) decoding（MK IV） 3. Frame Synchronization detection and frame header information extraction 4. CRC checks and Parity check(MK IV） 5. Fanout（1 : 1、1 : 2、1 : 4） 6. Output buffer

DATA D + CLK ……111111110111111110111111110111111110…… sync pattern CRC checks Check &Strip off parity 1:1 15 X 8bit ACK 1:2 Ready WR_CLK FFT_CLK 1:4 SYSTEM_CLK MK V 数据通道 MK V Data MK IV data MK IV 数据通道 PBI Data Stream Frame sync、 Frame header Input buffer 8K X 32bit 8K X 32bit 15 X 32bit 15 X 32bit 15 X 8bit fanout NRZM decoding Data checks Output buffer

32M CLKPBI_1 PBI_1 DATA CLKPBI_2 PBI_2 DATA CLKPBI_5 PBI_5 DATA FFT & MAC Board Diagram 32M 160M D E L A Y F R I N G E FFT 16bits Scaled Fixed Point F S T C M A C Data Output LTA 7300A 16bits … 8M Model Input 32M MCC

FFT(Fast Fourier Transform) Done PING-PANG RAM Xilinx IP Core 1(b) 2(b) 3(b) 9 bits FFT 16 bits 1024 Fixed Point Index 1(a) RAM 16x2 x1024 2(a) RAM 16x2 x1024 3(a) RAM 16x2 x1024 Address FFT_R 10 bits 16 bits FFT_I 1 2 3 DATA_R DATA_I (16 bits)

Model Parameter • Integer Bit Delay • Fringe Stopping • FSTC(Fractional Sample Time Correction) N: Bit number in one model cycle M: FFT cycle in one model cycle a,b,c,d,e are calculated by MCC

MAC(multiple and accumulate) 42x2 bits X_R X_I 16 bits 1~1023次 R RAM 42x512 I RAM 42x512 Dout_R Dout_I 42x2 bits 42x2 bits 16 bits Acc RAM Y_R Y_I 1024次 R RAM 42x512 I RAM 42x512 DOUT_R = X_R * Y_R + X_I * Y_I DOUT_ I = X_I * Y_R - X_R * Y_I Output RAM

FFT & MAC Board ML402 Evaluation Platform (V4-SX35)

MCC FFT points size, Nyquist Frequency, Sky Frequency, Delay polynomial Parameters: a, b, c, d,e Model Parameters calculation (8 channels) Output Parameters From PPC Rs232 FIFO Powerpc (virtex4) GPIO

MCC Board ML405 Evaluation Platform (V4-FX20)

Result – TC-1 Satellite The Fringe of the SH-UR Baseline TC-1 observation with Integration time of 62.5 ms

Results - SMART-1 DVLBI observation

Results (Cont.)

Future Plan • VSI • FITS format

Thanks 

Chinese Real Time VLBI Correlator