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FEE Electronics progress

FEE Electronics progress. PCB layout progress VHDL progress in TBU Prototype fixture for software. PCB Layout Progress. April 30 th : 49% signals routed. June 9 th : 77% signals routed. Complete memory   95% complete – power and decoupling

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FEE Electronics progress

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  1. FEE Electronics progress PCB layout progress VHDL progress in TBU Prototype fixture for software

  2. PCB Layout Progress April 30th : 49% signals routed June 9th : 77% signals routed • Complete memory   95% complete – power and decoupling • Gbit Ethernet.  90% complete – power and decoupling • ADC output signals to the FPGA.   100% complete • Discriminator signal connections to the FPGA   100% complete • Mezzanine connector signal definition   60% complete • Clock distribution to the ADCs   100% complete • Power supply blocks and delivery planes. • FPGA configuration memory. • Temperature sensors, RS232, LEDs etc.

  3. PCB layout targets • June 30th : • Complete routing and layout. • Submit to manufacturer for validation and quote. • Submit to assembler for evaluation of assembly and final parts purchase. • July 7th : • Complete engineering review. • July14th : • Submit to pcb manufacturer and assembler. • August 17th : • Assembled FEE64 delivered.

  4. Collaboration with Detector Systems Development Group of TBU.(Technology Business Unit ) Currently : • Gbit data rate from memory on the devkit => 240Mbit/sec . • System boots with fallback to golden copy. • Pin allocation of FEE64 memory and Gbit signals checked. Next steps : • Create a DMA peripheral and check performance. • Create a memory test and configuration system.

  5. Prototype fixture for softwaredevelopment • Pin out and advice provided by Steve Thomas. • Fixture will allow communications between the ASIC and Linux to be developed. • Mux readout logic VHDL can also be developed. • Design and manufacture of fixture in progress in DL electronic workshops. • Delivery mid June. Fixture comprises a ZIF socket on a pcb designed to mount a packaged ASIC onto an ML507 FPGA development board.

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