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A Probabilistic Approach to Logic Equivalence Checking

A Probabilistic Approach to Logic Equivalence Checking. Chun-Yao Wang ( 王俊堯 ) Dept. CS NTHU 2006. 01. 06. Outline. Introduction Previous Work Probabilistic Logic Equivalence Checking Exact Approach Approximate Approach Experimental Results Conclusions. Motivation.

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A Probabilistic Approach to Logic Equivalence Checking

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  1. A Probabilistic Approach to Logic Equivalence Checking Chun-Yao Wang (王俊堯) Dept. CS NTHU 2006. 01. 06 1

  2. Outline • Introduction • Previous Work • Probabilistic Logic Equivalence Checking • Exact Approach • Approximate Approach • Experimental Results • Conclusions 2

  3. Motivation • Logic equivalence checking • Logic optimization, scan insertion, manual modification • Exhaustively simulation is infeasible for practical designs 3

  4. Problem Formulation • Given two netlists N_ori,N_opt • N_ori is the original netlist • N_opt is the netlist after area/timing optimization (restructuring) • The problem is to formally verify the equivalence of N_ori and N_opt 4

  5. Outline • Introduction • Previous Work • Probabilistic Logic Equivalence Checking • Exact Approach • Approximation Approach • Experimental Results • Conclusions 5

  6. 1 - a a a a b b a 1 - (1 - a)  (1 - b) = a + b - a  b b Previous Work(1/3) • Probabilistic based approach • Assume circuits only consist of AND/OR/NOT gates • Probability formulae (independent signals) • Symbol represents the probability of signal one 6

  7. a × (1-b) a a × (1-b) + b ×c – a × (1-b) ×b ×c = a×(1-b) + b×c– a×(b-b2)×c = a×(1-b) + b×c– a×(b-b)×c = a×(1-b) + b×c b 1-b c b × c E. J. McCluskey et al, "Probabilistic treatment of general combinational networks," IEEE Trans. Computer, June 1975 Previous Work(2/3) • Assign the probability symbol to PIs • Derive probability expressions • Perform exponent suppression ( xm→ x ) on reconvergent gates • Compare the output probabilities (unique) • Problem: Representation complexity 7

  8. J. A. Abraham et al, " Probabilistic design verification ," ICCAD, 1991 Previous Work (3/3) • Assign real numbers as input probabilities instead of symbols • Evaluate output probability (number) of circuits • Arithmetic operations • Problems: • Aliasing occurrence • Signal correlation 8

  9. N2 N1 Aliasing Problem • Two different circuits have the same output probability • Example: • N1≡N2, but with the same output probability • Multiple runs increase the confidence level 9

  10. ( × ) A G1 B G2 ( ○ ) Signal Correlation Problem • Numbers cannot be assigned immediately • Numbers should be assigned after exponent suppression • Example: • Two inputs of G2 are correlated with signal B • Without considering exponent suppression • Considering exponent suppression 10

  11. Outline • Introduction • Previous Work • Probabilistic Logic Equivalence Checking • Exact Approach • Aliasing-Free Probability Assignments • Encoding Scheme and Alternative Operations • Dealing with Signal Correlation • Internal Tree-Structure Replacement • Approximate Approach • Experimental Results • Conclusions 11

  12. Teslenko, M., Dubrova, E., and Tenhunen H., "Computing a perfect input assignment for probabilistic verification", EMT'2005, May 12-15 Aliasing-Free Probability Assignments • An aliasing-free assignment • xi= • ai+1=(ai-1)2+1, a1>=3 &  Z+, i=1~n-1 • Problem: • The assignments grow exponentially • n <= 24 is feasible • Examples: • x1 = , x2 = , x3 = , …, x6 = , … 12

  13. Why Aliasing-Free • A 3-input function has distinct functions • Assume x1 =, x2 = , x3= • The probability of each function is distributed from ~ X1 X2 0 0 1 0 0 1 1 1 X3 0 1 13

  14. Encoding Scheme • Denominators are either ai or the product of ai • , , • Suppose the weight of bit-i is ai • Multiplication replaces addition • Reduce memory usage • Examples: • x1 = = = • x2 = = = • x3 = = = • x1 × x2 × x3 = × × = ( ) 14

  15. ( ) ( ) = ( ) ( ) ( ) = Example – AND Gate • Original formulation • Bitwise-AND (∩) operation 15

  16. Shift-Add Operation • When transforming two input probabilities to their equivalent probabilities • Denominators are either 3, 5, 17, …, • Shift-add operations are used to obtain the numerator instead of multiplication operations • Example: • Numerator 5 = 1 × 5 can be obtained by ( 0001 << 2 ) + 0001 = 0101 = 5 ( ) ( ) = 16

  17. ( ) = ( ) ( ) ( ) = ( ) Example – OR Gate • Original formulation • Bitwise-OR (∪) operation 17

  18. ( ) ( ) = A B G1 ( ) G3 C G2 ( ) = ( ) Dealing with Signal Correlation • When transforming two input probabilities to their equivalent probabilities • The lowest common multiple suppresses the correlation of two input probabilities if the denominators have the same factor 18

  19. ≡ Internal Tree-Structure Replacement • Example: • Verify if N1≡ N2 • Only two input assignments and are used A A G1 G1 B B G2 G2 C C N1 N2 19

  20. Outline • Introduction • Previous Work • Probabilistic Logic Equivalence Checking • Exact Approach • Aliasing-Free Probability Assignments • Encoding Scheme and Alternative Operations • Dealing with Signal Correlation • Internal Tree-Structure Replacement • Approximate Approach • Experimental Results • Conclusions 20

  21. L1 L2 S1 S2 aliasing-free assignments aliasing-free assignments R P G ︰ R P G ︰ : ︰ Approximation Structure • Connect Random Probability Generator (RPG) to DUV • Aliasing-free assignments are assigned to RPG’s PIs • RPG produces every possible function • |PO| in RPG = |PI| in DUV • Verify the equivalence of S1 and S2 Verify the equivalence of L1and L2 21

  22. Problem Formulation • Given two large netlists S1,S2 (# of required input assignments > 24) • The problem is to verify the equivalence of S1 and S2 withaliasing rate (ε) • ε  pr(S1S2 ∩ L1L2) 22

  23. L1 L2 S1 S2 aliasing-free Assignments aliasing-free assignments R P G ︰ R P G ︰ : ︰ r r n n Analysis(1/3) • Assume r (resource) input assignments are available, and S1, S2 (DUVs) have n PIs. What is the aliasing rate ε in using ApproximationStructure to verify the equivalence of S1 and S2? 23

  24. L1 S1 2/15 R P G 7/15 1/3 1/5 9/15 Analysis(2/3) • r=2, n=3, connect 2/15, 7/15, 9/15 to the inputs of S1 • Uniformly hash 16 S-functions to one L-function • ε  24

  25. Analysis(3/3) • ε  pr(S1 ≠ S2 ∩ L1 = L2) = pr(L1 = L2) - pr(S1 = S2) = - • Assume n>24 ( ), εis simply related to r • r=8, ε 10-77 • r=9, ε 10-154 • r=10, ε 10-308 • r=11, ε 10-616 • r=12, ε 10-1233 L1=L2 S1=S2 25

  26. Outline • Introduction • Previous Work • Probabilistic Logic Equivalence Checking • Exact Approach • Approximate Approach • Experimental Results • Conclusions 26

  27. Experimental Results – exact approach 27

  28. Circuits |PI| |PO| n=Max TFI|PI| RPG |PO| Time (s) Mem. (MB) C432 36 7 36 6 0.32 7.39 C499 41 32 41 32 1.71 6.27 C880 60 26 45 9 0.26 5.16 C1355 41 32 41 32 2.21 6.96 C1908 33 25 33 25 1.37 6.64 C2670 233 140 122 10 1.15 8.52 C3540 50 22 50 17 4.69 9.38 C5315 178 123 67 66 0.25 8.34 C6288 32 32 32 21 29.41 18.00 C7552 207 108 194 46 3.71 11.00 Experimental Results – approximate approach (r=10, ε 10-308) 28

  29. Outline • Introduction • Previous Work • Probabilistic Logic Equivalence Checking • Exact Approach • Approximate Approach • Experimental Results • Conclusions 29

  30. Conclusions • An aliasing-free assignment procedure is proposed • More efficient operations, such as bitwise-AND, bitwise-OR, and shift-add operations are used • The aliasing-free assignment and bitwise operations deal with the signal correlation problem well • Internal tree-structure replacement is used to reduce the number of required input assignments • An approximate approach with configurable aliasing rate is proposed for large circuits 30

  31. Appendix • P.31~P.37 31

  32. Calculate Signal Probability • Transform two input probabilities to their equivalent probability • The denominator is the lowest common multiple of the original denominators • The two new numerators conduct bitwise-AND/ bitwise-OR operation to obtain the numerator of output probability if it is an AND/OR gates 32

  33. (1- ) (1- ) (1- ) (1- ) Why Work – AND Gate • The operation0101∩0011is analogous to perform intersection on minterm sets ( ) ( ) = ( ) ( ) ( ) = X2 X1 bitwise-AND prob. of minterm × = • 0 • 1 • 0 • 1 • 0 • 0 • 1 • 1 • 0 • 0 • 0 • 1 • 0 0 • 0 1 • 0 • 1 1 × = ∩ = × = × = 33

  34. (1- ) (1- ) (1- ) (1- ) ( ) = ( ) ( ) ( ) = ( ) Why Work – OR Gate • The operation10001∪00101is analogous to perform union on minterm sets X2 X1 prob. of minterm bitwise-OR • 0 • 1 • 0 • 1 • 0 • 0 • 1 • 1 • 0 • 1 • 1 • 1 • 0 0 • 0 1 • 0 • 1 1 × = × = ∪ = × = × = 34

  35. Internal Tree-Structure Replacement (1/2) • Only consider two Boolean networks for verification • Internal tree-structure replacement can be used to reduce the number of required assignments • The output probability is changed, but it does not affect the judgement on the equivalence checking 35

  36. Analysis (2/3) • pr(S1 = S2) = • pr(L1 = L2) = • If S1=S2, then L1=L2 • (1) pr(S1 = S2 ∩ L1 ≠ L2) = 0 • pr(S1 = S2 ∩ L1 = L2)+pr(S1 = S2 ∩ L1 ≠ L2)=pr(S1 = S2) = • (2) pr(S1 = S2 ∩ L1 = L2) = • (3) ε pr(S1 ≠ S2 ∩ L1 = L2)=pr(L1 = L2) - pr(S1 = S2) = - • (4) pr(S1 ≠ S2 ∩ L1 ≠ L2) = 1 – pr(L1 = L2) = 1 - • (1) + (2) + (3) + (4) = 1 L1=L2 L1=L2 S1=S2 S1=S2 36

  37. Experimental Setup • Benchmarks • n<=24exact approachMCNC benchmarks in BLIF format • n>24approximate approach ISCAS-85 benchmarks in BLIF format • Environment • SIS environment • Sun Blade 2500 workstation • Experimental flow • Map benchmarks to the SIS library (22-1.genlib), decompose the networks to AND/OR/NOT gates • Verify the equivalence between original Netlist and Netlist after area optimization (map –m0) • Separate multiple-output network into many single-output subnetworks • BDD based approach - ntbdd_verify_network( N1, N2, DFS_ORDER, ONE_AT_A_TIME ) 37

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