Digital Integrated Circuits A Design Perspective

1. 1 Digital Integrated CircuitsA Design Perspective

2. 2 The Wire

3. 3 Interconnect Impact on Chip

4. 4 Wire Models

5. 5 Impact of Interconnect Parasitics Interconnect parasitics reduce reliability affect performance and power consumption Classes of parasitics Capacitive Resistive Inductive

6. 6 Nature of Interconnect

7. 7 INTERCONNECT

8. 8 Capacitance of Wire Interconnect

9. 9 Capacitance: The Parallel Plate Model

10. 10 Permittivity

11. 11 Fringing Capacitance

12. 12 Fringing versus Parallel Plate

13. 13 Interwire Capacitance

14. 14 Impact of Interwire Capacitance

15. 15 Wiring Capacitances (0.25 mm CMOS)

16. 16 INTERCONNECT

17. 17 Wire Resistance

18. 18 Interconnect Resistance

19. 19 Dealing with Resistance Selective Technology Scaling Use Better Interconnect Materials reduce average wire-length e.g. copper, silicides More Interconnect Layers reduce average wire-length

20. 20 Polycide Gate MOSFET

21. 21 Sheet Resistance

22. 22 Modern Interconnect

23. 23 Example: Intel 0.25 micron Process

24. 24 INTERCONNECT

25. 25

26. 26 The Lumped Model

27. 27 The Lumped RC-ModelThe Elmore Delay

28. 28 The Ellmore DelayRC Chain

29. 29 Wire Model

30. 30 The Distributed RC-line

31. 31 Step-response of RC wire as a function of time and space

32. 32 RC-Models

33. 33 Driving an RC-line

34. 34 Design Rules of Thumb rc delays should only be considered when tpRC >> tpgate of the driving gate Lcrit >> ? tpgate/0.38rc rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line trise < RC when not met, the change in the signal is slower than the propagation delay of the wire