Digital Integrated Circuits A Design Perspective

1. Digital Integrated CircuitsA Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices

2. Goal of this chapter • Present intuitive understanding of device operation • Introduction of basic device equations • Introduction of models for manual analysis • Introduction of models for SPICE simulation • Analysis of secondary and deep-sub-micron effects • Future trends

3. B A Al SiO 2 p n Cross-section of pn -junction in an IC process A Al A p n B B One-dimensional representation diode symbol The Diode Mostly occurring as parasitic element in Digital ICs

5. Diode Current --current increases by a factor of 10 for every extra 60 mV of forward bias

6. Forward Bias

7. Reverse Bias

8. Models for Manual Analysis VDon depends upon IS, a value of 0.7 V is typically assumed. IS is proportional to the area of the diode, and a function of the doping levels and widths of the neutral regions 10-17 A/um2.

9. Junction Capacitance/ Depletion layer capacitance The capacitance decreases with an increasing reverse bias

10. Secondary Effects 0.1 ) A ( 0 D I –0.1 –25.0 –15.0 –5.0 0 5.0 V (V) D Avalanche Breakdown --The value of Ecrit is approximately 2 *105 V/cm

11. Diode Model

12. SPICE Parameters

13. |V | GS A Switch! An MOS Transistor What is a Transistor?

14. The MOS Transistor Polysilicon Aluminum

15. MOS Transistors -Types and Symbols D D G G S S Depletion NMOS Enhancement NMOS D D G G B S S NMOS with PMOS Enhancement Bulk Contact

16. Threshold Voltage: Concept

17. The Threshold Voltage

18. The Body Effect

19. -4 x 10 6 VGS= 2.5 V 5 Resistive Saturation 4 VGS= 2.0 V Quadratic Relationship (A) 3 VDS = VGS - VT D I 2 VGS= 1.5 V 1 VGS= 1.0 V 0 0 0.5 1 1.5 2 2.5 V (V) DS Current-Voltage RelationsA good transistor

20. Transistor in Linear

21. Pinch-off Transistor in Saturation

22. Current-Voltage RelationsLong-Channel Device

23. A model for manual analysis

24. -4 x 10 2.5 VGS= 2.5 V Early Saturation 2 VGS= 2.0 V 1.5 Linear Relationship (A) D I VGS= 1.5 V 1 VGS= 1.0 V 0.5 0 0 0.5 1 1.5 2 2.5 V (V) DS Current-Voltage RelationsThe Deep-Submicron Era

25. Channel Length Modulation

26. 5 u = 10 sat ) s / m ( n u x = 1.5 x (V/µm) c Velocity Saturation Scattering, collisions Constant velocity Constant mobility (slope = µ)

27. Perspective I D Long-channel device squared V = V GS DD Short-channel device linear V V - V V DSAT GS T DS

28. Mobility Degradation

29. -4 x 10 -4 x 10 6 2.5 5 2 4 1.5 (A) 3 (A) D D I I 1 2 0.5 1 0 0 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 V (V) V (V) GS GS ID versus VGS linear quadratic quadratic Long Channel Short Channel * Subthreshold conduction

30. Subthreshold Slope

31. -4 -4 x 10 x 10 2.5 6 VGS= 2.5 V VGS= 2.5 V 5 2 Resistive Saturation VGS= 2.0 V 4 VGS= 2.0 V 1.5 (A) (A) 3 D D VDS = VGS - VT I I VGS= 1.5 V 1 2 VGS= 1.5 V VGS= 1.0 V 0.5 1 VGS= 1.0 V 0 0 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 V (V) V (V) DS DS ID versus VDS Long Channel (Ld=10um) Short Channel(Ld=0.25 um)

32. -4 x 10 0 -0.2 -0.4 (A) D I -0.6 -0.8 -1 -2.5 -2 -1.5 -1 -0.5 0 V (V) DS A PMOS Transistor VGS = -1.0V VGS = -1.5V VGS = -2.0V Assume all variables negative! VGS = -2.5V

33. Transistor Model for Manual Analysis

35. A similar result can be obtained by just averaging the values of the resistance at the end points (and simplifying the result using a Taylor expansion):

38. MOS CapacitancesDynamic Behavior

39. Dynamic Behavior of MOS Transistor

40. Dynamic Behavior of MOS Transistor • The capacitances originate from three sources: the basic MOS structure, the channel charge, and the depletion regions of the reverse-biased pn-junctions of drain and source. • Aside from the MOS structure capacitances, all capacitors are nonlinear and vary with the applied voltage, which makes their analysis hard.

41. Polysilicongate Source Drain W x x + + n n d d Gate-bulk L d overlap Top view Gate oxide t ox + + n n L Cross section MOS Structure Capacitances :The Gate Capacitance it is useful to have Cox as large as possible lateral diffusion

42. Gate Capacitance Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off The gate-capacitance components are nonlinear and varying with the operating voltages. To make a first-order analysis possible, we will use a simplified model with a constant capacitance value in each region of operation.

43. Gate Capacitance When increasing VGS, a depletion region forms under the gate. This seemingly causes the thickness of the gate dielectric to increase, which means a reduction in capacitance. Capacitance as a function of the degree of saturation Capacitance as a function of VGS (with VDS = 0) The large fluctuation of the channel capacitance around VGS=VT is worth remembering. A designer looking for a well-behaved linear capacitance should avoid operation in this region. [Dally98]

45. Measuring the Gate Cap

46. Assignment-4 - Find the gate capacitances of NMOS and PMOS devices used in the inverter of Assignment-1 using SPICE simulations. - Obtain the inverter characteristics by incorporating these capacitances in the simulation. Report any differences.

47. Diffusion/Junction Capacitance - bottom-plate junction - side-wall junction

48. Channel-stop implant • Channel-stop implant required to prevent parasitic mosfets. • Prevents conduction between unrelated transistor sources and drains (and wells). Two n+ regions and the FOX from a transistor. FOX is thick, therefore transistor has a large Vth. Nonetheless, a sufficiently positive potential on the interconnect line will turn on the transistor slightly (causing a leakage path). Channel-stop implant raises Vth of parasitic transistor to a very large value.

49. Since all these capacitances are small-signal capacitances, we normally linearize them and use average capacitances

50. Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest