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Solar Probe Plus FIELDS Quarterly Management DCB_RFS-ADC July 18, 2013

Solar Probe Plus FIELDS Quarterly Management DCB_RFS-ADC July 18, 2013. FPGA Daughter Board Development. FPGA ETU Daughter board schematics and layout completed This board houses the Actel/ Microsemi reprogrammable FPGA (ProASIC3000)

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Solar Probe Plus FIELDS Quarterly Management DCB_RFS-ADC July 18, 2013

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  1. Solar Probe Plus FIELDS Quarterly Management DCB_RFS-ADC July 18, 2013

  2. FPGA Daughter Board Development • FPGA ETU Daughter board schematics and layout completed • This board houses the Actel/Microsemi reprogrammable FPGA (ProASIC3000) • Fabrication and population scheduled to accommodate integration with DCB-RFS_ADC ETU1 • HDLP Connectors delivery expected in September, 2013 ETU FPGA Daughter board layout Daughter board de-insertion hardware

  3. DCB/RFS_ADC ETU1 Development • DCB_RFS-ADC Schematics Completed • Schematic Review held in June, 2013 • BOM released and parts have been ordered • DCB_RFS-ADC PCB Layout Completed Boards can be driven by the RFS Frontend ETU1 boards (will be eventually integrated during the ETU2 stage) Instrument & LNPS I/Fs S/C I/F RFS ADCs and Data Buffers RFS Memory (SRAM) We are checking the layout & expect to have boards in August, 2013. FPGA Daughter Bd CPU Memory: SRAM, EEPROM & PROM FLASH

  4. DCB/RFS_ADC ETU1 BOM • Most parts are “flight-like” or high-fidelity commercial equivalents on order • Linear Power supply (non-flight) replaces LNPS for ETU1 • Digital I/F to LNPS is included • Instrument I/Fs (to DFB, AEB and MAG-O) are included • HDLP Connectors (mother to daughter board) may be the gating item • But FPGA Development/Simulation is ongoing during this “waiting period” • Design & fabrication of an SRAM adapter (for use of commercial parts) is underway

  5. DCB/RFS_ADC Revised Power Estimate • DCB and RFS have been combined into one board and one FPGA • Revised Power Estimates include scenarios for DCB (1.6W Avg) only and DCB with RFS subsystem (2.6W Avg). • We expect to be able to operate without the ADC External Reference, but have included this as an option on ETU1

  6. DCB/RFS_ADC FPGA • DCB related subsystems are well-known (Coldfire Processor has been used for the MAVEN DCB). • The DCB portion of FPGA utilization is estimated at approximately 30%. • RFS utilization estimated at approximately 40% of the FPGA gates. FPGA SRAM is allocated for filter coefficients and high-speed temporary storage.

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