Particles and Fields Package Quarterly Status Review (QSR) April 19, 2011. Dave Curtis, PFP PM. SSL Contracting Status. Funded through the end of April More info in the Business Splinter presentation. Schedule Status. EMs have made a lot of progress this month
Quarterly Status Review (QSR)
April 19, 2011
Dave Curtis, PFP PM
Funded through the end of April
More info in the Business Splinter presentation
EMs have made a lot of progress this month
All EM PWBs in test but ~2 (HVPS boards, in fab)
SEP, LPW, SWEA, MAG EM mechanical assembly complete
STATIC EM TDC complete random vibe
SWIA/STATIC analyzers parts out to fab
EM Package I&T in progress
LPW, SEP, SWEA test with PFDPU complete
EM ‘Early Payload Test’ with LM complete
MAG next week
Pushing to complete before CDR
EM Instrument calibrations don’t complete till after Package I&T
STATIC is on critical path
13.6 weeks margin to delivery
Driven be delays in EM I&T
Status at instrument CDR
SWIA, STATIC EM will not be complete
SWIA, STATIC attenuator life test not done
SWIA, STATIC power converters may still be in test
Rest of instrument EM will be complete, with perhaps some system level test still in progress
LPW, SEP, SWEA EM integrated with PFDPU EM
PFDPU EM Early Payload test with Spacecraft EM
SWEA Peer Review Completed
STATIC Random Vibration Completed
SEP Attenuator Life Test Completed
More in instrument sections…
Supporting Project planning process
Supporting EMC, Payload, SDT working groups
Completing EM board testing
Completing SWIA/STATIC EM mechanical part fabrication
Complete PF Package EM I&T
Prepare for CDR
HV801 issue still open
Current plan is to buy HV801s from LADEE NMS, who has parts on order they no longer need.
We still don’t have the parts in hand
Working on an analysis to decide if the PFDPU mechanical design needs to be augmented to support the PWBs to avoid excessive displacements in vibe
Analysis complete, passed on to GSFC expert for review.
LPW Stacer Plating issue (NEW)
After plating stacer with black Nickel it no longer stows properly
Need plating for thermal reasons (aeroheating, thruster heating)
Historically we have used a paint (DAG213), but that will not survive atomic oxygen at Mars
Working with GSFC Materials on possible solutions
Received ‘Thermal Memos’ as well as spacecraft thermal model
Some of the instruments are in trouble according to the thermal memo
For example, STATIC goes to -100C
We are working on identifying if the issue is the model or the design
Our preliminary results are more benign
P-20 reduced (mating procedure)
CCR262 approved to reallocate NTE amongst PFP
Small increase in MAG power
Small decrease in SWEA power.
Per 2009-6-9 allocations from Bruce
New MAG requirements on telemetry formatting puts MAG 4% over allocation
CCR (265) to update PFP Functional Requirements (Level 3) approved
some old requirements need updating
Verification matrix mostly complete
Have Functional, ERD, ICD requirements complete, in review
Boot software verification has started
against software level 5 requirements, which link back to FRD and ICD.
STATIC TOF EM Acoustics and Vibration test complete
All but coarsest grid with thinnest foils passed
Will not use coarsest grids
Will repeat on full EM and FM
EM Interface tests started
Reduces risk, not a qualification test
SEP Attenuator Mechanism Life Test complete
SEP Attenuator life test complete
4100 cycles on EM twice expected life
~1000 in air, ~3000 in vacuum
Will collect some more cycles over the next few months
SWIA, STATIC attenuator life test pending completion of EM attenuator
SWEA door mechanism identical to STEREO
SWEA, STATIC door mechanism functional, life test pending
LPW relay life test expected to start soon
LPW deployment life test expected to start soon
Stacer coating problem holding that up
Connerney, Sheppard, Schnurr, Oliversen, Espley, etc.
EM sensor assembly, pigtail, GSE sensor harness completed.
Breakout PWBs fabrication completed.
Draft MAG Flight Software Requirements Specification (for PFDPU).
Completed Safe-to-Mate procedures for MAD board (MAVEN-MAG-PROC-0026).
Completed EM Magnetometer board scale factors calibration at GSFC 22’ MAG Test Site; scale factor resistors installed on board.
FPGA (rev 0) burned at Aeroflex, received and installed on MAD board. Functional testing in progress.
GSE (UCB emulator) development continues; CMD and TLM successfully flowing between GSE and MAD board.
Sensor non-magnetic heaters design received from vendor (Tayco), under review.
Frames for MAD board and ACHE board fabricated at GSFC; boards installed in frames (see pix).
MAG Analog and Digital (MAD) Board & frame
A/C Heater Electronics
(ACHE) Board in frame ->
Mature MAG software requirements draft w/UCB.
Hypertronics KPC120 connectors installation and mating issues.
Radiation test plan for MIL spec CD4066 quad bilateral switches completed; testing scheduled to begin April 18, 2011.
Integration and test of MAG (MAD board and sensor) w/ PFDPU at UCB scheduled April 26-28, 2011.
MAD board frame modifications (test connector placement, mechanical mod for center board support) pending final approval.
Continue winding FM sensor ring cores, feedback/sense bobbins, and magnetic piece parts per technician availability; fabricate sensor assembly terminal boards.
Draft worst case analysis of MAD board.
MAG Peer Review scheduled for May 5, 2011 @ GSFC.
Workload: RBSP FM post-environmental test evaluation drags on; Juno FM system integration work in progress @ Astrotech, KSC.
Jasper Halekas, SWIA Lead
Pseudo Data Products
Test pulser output
divided by four ratios,
sent to alternating
3-d Sky Plot
Dave Mitchell, SWEA Lead
SWEA parts plated with high-P electroless black-Ni
Magnetic screening station at SSL
SWEA Electronics I&T
STEREO SWEA EM front-end boards
Jim McFadden, STATIC Lead
Carbon foils mounted in TOF units survive vibration test – automated software used to evaluate foil breakage
Ordered carbon foils on mica slides to improve mounting yield
The design of START foil grid-frames was modified to compensate for poor clamping due to fabrication tolerances - new grid-frames ordered.
Design of attenuator motor completed, drawings for ETU in process
Energy analyzer/deflector parts drafted and ordered
EM TDC board bench testing complete, part modifications made
EM preamp 1 modified and working adequately for integration w/ TDC board – will be used while optimized preamp board is developed
EM Anode, Preamp and TDC boards integrated – working
EM Digital board passed power and PFDPU simulator interface testing, ready for interface test with TDC
EM Sweep HV board partly loaded and in test (see pictures)
Clean room equipment installed – racks, SS table, GN2 purge, etc.
Helmholtz coil template fabricated, waiting on welding before assembly
One of two TOF electrical connections broke in 1 of the 3 units during vibration test (see pics) – connection redesigned for stress relief
Mounting fixtures for handling flight carbon foil frames need to be fabricated before additional EM carbon foils are loaded
New START foil grid-frames will require inspections after fabrication
Preamp design changes nearly complete for optimal dynamic range – may require new layout
EM 15kV-MCP board changed, MCP “stack stick” multiplier abandoned in favor of a pair of VMI multipliers and a tapped transformer – EM waiting on part placement changes (Berg).
Digital board FPGA still in development
EM LVPS loaded – waiting to be tested
Manipulator fixtures for calibration chamber testing in development
Some test harnesses and test cables still on order
New calibration chamber ordered – delivery late May
SS sink for clean room assembled – waiting for drain assembly
Davin Larson, SEP Lead
Mechanical attenuator tests completed
~4500 cycles completed (all but ~1000 in vacuum)
Integration of DAP board (& ½ sensor sans detectors) with PFDPU begun on 2011-04-11
Safe to mate –ok
Initial power on - ok
but receiving +6V and -6.3 volts instead of nominal +/- 5V
Command test – ok
Successfully turned on test pulser
Bias voltage setting not working (not yet functional on DAP?
Telemetry tests – ok
Successful run of ‘SEP_DAPINIT’
Unbalanced analog voltages result in offset from baseline
Successful run of “SEP_THRESH_SWEEP”
Successful run of “SEP_TPSWEEP”
Some cross talk visable that was not seen with MISG
Noise level is substantially larger and assymetric
Timing Tests – skipped
SEP Aperture tests – ok
SEP auto aperture closure – problem on REG
SEP power inrush current test - OK
ETU Silicon detectors (1 stack) delivered on 2011-04-12.
3 channels loaded on DAP #1
12 channels loaded on DAP #2
Actel programming: Using FPGA version 0x32
Data collected through PFDPU in APID 30
Life tests were done on 3 separate days.
TCP/IP connection from computer to MISG was unreliable.
Difference in actuation time is probably temperature related.
Tested the range of bus voltages that would cause actuation.
Below 22 V (2.08 V across nanomuscle), actuation failed in air.
What voltage to use for +/- 5VA supply.
Analog supply NOT currently regulated
Need secondary regulation for A250?
Eliminate requirement of 5V Digital altogether
Mods needed for flight DAP board:
Use faster transisters on pulse generator (fixes 3.3 volt logic problem)
Use 2.5V reference instead of 5VA for baseline trim
Use Valid signal for hysteresis on peak detect
Gain change on peak detect circuit (perhaps not needed now)
Switch from 10 MΩ to 1MΩ resister on bias voltage control
5 MΩ resistor to -5VA (-2.5R?) to correct for OpAmp input current (this mod is questionable if BLRena mode is working properly)
Insert caps on attenuator lines to clean up some noise
FPGA Mods from version 0x32
Eliminate secondary pulse by applying BLRena for 6 μsec on test pulse return
Extend test pulse duration from 10 μsec to 20 μsec
16 bit counters on no peak counters
Ability to turn off housekeeping measurement
Event mode resolution
Purchase new nimbin and test pulser to replace AWOL test pulser
Test for correct coincidence determination with FPGA
New radiation source
Cross talk observed in PFDPU but not MISG?
Increased Noise observed in PFDPU (probably resolved with shield boards)
Telemetry dropouts from PFDPU science packets
Possible change in opto coupler wiring of actuator control on DCB to eliminate any possibility of noise
Baseline shift at high count rates – (probably not an issue)
1 mv shift in baseline shortly after the 1 pps signal
More to come
PFDPU Overall Integration
Functional and electrical verification ongoing
Actuator Control, Housekeeping, Instrument Current Monitoring
Verified LPW signal routing through IIB and Low Voltage Power Supply
DCB/REG/IIB/LPW (see next page)
Upcoming PFDPU integration tests
Remaining power services and signal routing to be checked on a per instrument basis
Power-switch, current monitoring on REG
Operation of LPW via the Supplies IIB LVPS
LPW/DCB Interaction via serial interface
Operation of the EUV Door Actuator
LPW Data analyzed for noise and anomalies
10 Hz – 4Vpk-pk
1KHz – 4Vpk-pk
100KHz – 4Vpk-pk
PFDPU – S/C Interface Test
DCB/REG Verification at Lockheed-Martin
Integrated power subsystem
Inrush current characterized
Tested S/C Discrete commands and Side Select
Reset, TIME commands verified
Operated PFDPU with the Lockheed-Martin Spacecraft Emulator
Verified signal protocol of RS422 command and telemetry interfaces
Operation with Flight Software – sent a variety of packets in order to work through the checksum generation algorithm. FSW is working this issue with Lockheed-Martin.
DCB ETU Build
DCB ETU #2 Build complete
Delivered (along with FLASH FPGA daughter board)
Short on main DCB power supply (3.3V)
Problem needs to be identified and fixed
Changes added to support the S/C interface modifications
Functional design is complete; undergoing life-test with flight software and PFDPU Integration
MISG Instrument Simulator
First cut operational instrument simulator delivered
uses the MISG-FPGA Block RAM
Implements the final Instrument Mode functionality
covers all 8 Instrument Interfaces
with a subset of the final pattern generator buffer space
Use MISG based SDRAM for Instrument Pattern storage (allowing for increased buffer space)
Incorporate new modules into next MISG-FPGA release
Software updated to handle special case where calculated checksum equals zero. When this occurs checksum is set to 0xFFFF
Python modules added to perform checksum processing and verification on PFDPU telemetry
Python module added to support PFDPU Memory Loads
Delivered first rev of STATIC configuration
Created Python module for playing back raw data over TCP link with GSEOS
Supported LPW EM integration testing
We are working on a second PCB layout for the REG board ETU#2 due to a connector mis-wiring issue on the first layout. This re-layout process has begun.
The REG board tester was built and is now in operation
All REG based switchable services have been tested
Still pending: adjustment/tuning of the current monitoring subsystem; complete verification of the digital portion of the circuit
REG Board system checkout via PFDPU I/F Tests
DCB Interface/Housekeeping addressing
Instrument Power Switches
All power converter sections of the EM board have been tested with only the magnetics of MAG2 and off board connectors for STATIC, SWIA, and MAG left to be populated. (This excludes the MAG HEATER daughter boards from Goddard that are to be mounted on the IIB at a later date.)
The ±90V outputs on the LPW section sat at 114V when integrated with the system. This would indicate an unloaded state as the voltage would normally drop closer to ±90V when loaded (10mA peak).
The 5VD regulator on the SEP section will be changed to an LDO as the actual load is much lower with the system. The LTC1877 may have stability issues with such a low load.
ACTEL turn-off delay circuit for the LPW section will be added and tested on the EM board.
Optimization for noise, efficiency, and voltage levels will also be done after and in between integration.
One of the Hypertronics PC104 connectors delivered to us appear to have been assembled incorrectly
Connectors are very fragile, pins have bent and even broken during our ETU testing
We have implemented a mating procedure to mitigate this issue
We still need to verify the connection insertion is met with the boards installed in their frames
Schedule for testing is tight
As the integration progresses, we are finding issues that require resolution (e.g. power supply regulation, clock distribution). We need time to sort through all the open-items (hopefully prior to CDR) yet the individual subsystem testing/tuning is still ongoing.
April 12 2011