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ECE122 – 30 Lab 2: CMOS Design

The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering. ECE122 – 30 Lab 2: CMOS Design. Jason Woytowich September 9, 2005. Hierarchical Design Strategy. Complex designs should be broken down into manageable pieces. CPU.

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ECE122 – 30 Lab 2: CMOS Design

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  1. The George Washington UniversitySchool of Engineering and Applied ScienceDepartment of Electrical and Computer Engineering ECE122 – 30 Lab 2: CMOS Design Jason Woytowich September 9, 2005

  2. Hierarchical Design Strategy • Complex designs should be broken down into manageable pieces. CPU Bus Interface Register File Execution Unit Control Unit ALU FPU Adder Shifter Multiplier

  3. Hierarchical Design Strategy • Proper breakdown of the circuit decreases the difficulty of your design and testing. • Low level module implementations can be reused within the same design, or in other designs. • Low level modules can be replaced with functionally equivalent implementations.

  4. Lab activity – CMOS Buffer • Build a CMOS buffer out of CMOS inverter modules. Test your design.

  5. Gate Delay • Gate Delay is the amount of time it takes a change of input to appear as a change on the output. • Gate Delay is measured from the 50% point on the input signal to the 50% point on the output. Input Output tp

  6. Gate Delay • We also characterize the transition time of a signal. In this case we use the 10% and 90% points. 90% 10% tpLH 90% 10% tpHL

  7. Gate Delay • The load capacitance severely affects the gate delay. Inv1 Inv2

  8. Lab activity – Gate Delays • Using a single inverter as a load, find the gate delays of your inverter and your buffer. Check 0->1 and 1->0 transitions. tp

  9. SCMOS Library • Scalable CMOS Library • Contains (just about) every digital logic component you need to build anything. • And, Or, Xor, Nand, Nor, Xnor, Inv, Buf, Flip-flops, Pads, Capacitors, Resistors • Each of these components has a specific layout mapped to it. • It does not layout individual transistors.

  10. Lab activity – Gate delays • Compare the gate delays of the library buffer with yours. • Be sure to use the same load or the measurements are meaningless.

  11. Lab activity – Multiple inputs • Create a single test-bench which tests all the possible inputs to either the Nand, Nor or Xor gates.

  12. Voltage Transfer Characteristic • Vin on the X-Axis and Vout on the Y-Axis 5V Vout 0V 0V 5V Vin

  13. Homework • Using the ml2_125 model file, create an inverter so that it has a symmetric VTC. • Adjust only Wn and Wp. Keep Ln,p constant. Use a 10pF load. • Find the tpHL tpLH and tp for your inverter using the same inverter as a load. • Vary the size from 1 to 100 times the width in increments of 10. Keep (Wn/Wp) constant.

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