After mid-term review EE 334. Digital electronics. NMOS inverter CMOS inverter NMOS logic gates CMOS logic gates NMOS transmission gates CMOS transmission gates Sequential logic circuits NMOS flip flop CMOS flip flop J K flip flop.
Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.
Design is the heart of engineering. Throughout the course designing
concepts have been emphasized.
VO,, max= VOH =VDD-VTNL
The Figure demonstrate in present configuration more abrupt VTC transition region can be achieved even though the W/L ratio for the output MOSFET is small.
The rate at
For the NAND gate the effective length of the driver transistors doubles. That means the effective aspect ratio is decreased.
For the NOR gate the effective width of the drivers transistors doubles. That means the effective aspect ratio is increased.
NAND gate for more than three inputs is not attractive???
When A=B=logic 1
Both driver transistors are switched into nonsaturation region
and load transistor is biased in saturation region. We have
By substituting the values of current equation we can write as,
KL(VGSL-VTNL)2 = KDA[2(VGSA - VTNA)VDSA - VDSA2] + KDB[2(VGSB
-VTNB)VDSB - VDSB2]
Suppose two driver transister are identical, which implies that,
As we know VGSL=0
Also from figure VGSA=VGSB=VDD
By substituting all these parameters we can write above equation as,
(-VTNL)2 = 2(KD/KL)[2(VDD-VTND)V0-VO2)
Conclusion: The above equation suggested that when the both the driver are in conducting mode, the effectiveaspect ratio of the NOR gate is double. This further suggested that output voltage becomes slightly smaller when both inputs are high. Because higher the aspect ratio lower the output.
When all the inputs are high: design consideration!!
Three input NAND
Three input NOR gate design considerations
VOL = 0
VOH = VDD
Vout = 1
Vout = 0
Vin = 0
Vin = V DD
PMOS in non sat
PMOS in non sat
NMOS in sat
PMOS in sat
NMOS in non sat
PMOS in sat
NMOS in nonsat
Complete voltage transfer characteristics,
(i) VTN =|VTP|
(ii) K´n/2(W/L)=K´p/2 (W/L)
But K´n>K´p (because n>p)
How equation (ii) can be satisfied?
This can achieved if width of the PMOS is made two or three times than that of the NMOS device. This is very important in order to provide a symmetrical VTC, results in wide noise margin.
Case II: when the input is high and out put is low:
During switching all the energy stored in the load capacitor is dissipated in the NMOS device because NMOS is conducting and PMOS is in cutoff mode. The energy dissipated in the NMOS inverter can be written as,
The total energy dissipated during one switching cycle is,
The power dissipated in terms pf frquency can be written as
This implied that the power dissipation in the CMOS inverter is directly proportional to switching frequency and VDD2
Imax: depends on saturation current of devices
NML=VIL-VOL (noise margin for low input)
NMH=VOH-VIH (noise margin for high input)
NML=VIL-VOLU (noise margin for low input)
NMH=VOHU - VIH (noise margin for high input)
7 CMOS DeviceCMOS Logic Circuits
Large scale integrated CMOS logic circuits such as watched, calculators, and microprocessors are constructed by using basic CMOS NOR and NAND gates. Therefore, understanding of these basic gates is very important for the designing of very large scale integrated (VLSI) logic circuits.
8 CMOS DeviceCMOS NOR gate
CMOS NOR gate can be constructed by using two parallel NMOS devices and two series PMOS transistors as shown in the figure. In the CMOS NOR gate the output is at logic 1 when all inputs are low. For all other possible inputs, output is low or at logic 0.
For asymmetrical case switching time is longer
By recalling effective channel width and effective channel length concept we can effective conduction parameter for NMOS and PMOS for a CMOS NOR as,
Why we need
For NAND gate:
7 CMOS DeviceTransmission Gates
• In CMOS logic gate that a logic ‘1’ is transmitted unattenuated through the CMOS transmission gate in contrast to the NMOS transmission gate.
• Sequential Logic circuits; Characteristics of Dynamic Shift Registers and CMOS dynamic shift register.
S CMOS Device
GCharacteristics of NMOS transmission gate
If =VDD, VI=VDD, and initially, the output V0 is 0 and
capacitance CL is fully discharged.
Under these conditions, the terminal ‘a ‘acts as the drain because its bias is VDD, and terminal ‘b’ acts as the source because its bias is 0.
The gate to source voltage can be written as
As CL charges up and Vo increases, the gate to source voltage decreases. When the gate to source voltage VGS become equal to threshold voltage VTN, the capacitance stop charging and current goes to zero.
This implies that the
VO=VO(max) when VGS=VTN
VO(max) = VDD-VTN
This implies that output voltage never will be equal to VDD. ; rather it will be lower by VTN.
This is one of the disadvantage of an NMOS transmission gate when VI=high
CMOS transmission gate
GCharacteristics of a CMOS Transmission gate (Cont.)
the NMOS transmission gate cuts
off and IDN=0.
However, PMOS transistor
continue to conduct, because
VGSP of the PMOS is a constant
(VGSP=VDD). In PMOS transistor
IDP=0, when VSDP=0, which would be
possible only, if,
VO = VI = 5V
This implies that a logic ‘1’ is
transmitted unattenuated through
the CMOS transmission gate in
contrast to the NMOS transmission
NMOS transmission gate
As VO1 goes high, VO2 goes low.
If 2 is high low will transmitted through MN2 and VO4 would be at logic 1. Thus logic 1 shifted from input to output.
In shift register the input signal is transmitted, or shifted, from the input to the output during one clock cycle.
When the CMOS transmission gate turn off (=0), the pn junction
in the MN1 transmission gate transistor is reverse biased.
Close loop condition?
V condition?0=V1-i2R2=0 - (VI/R1)R2
i1 = i2
i condition?1=VI/R1, this current also flow through the capacitor
, causing charge to accumulate on VC.
At time t, the charge Q at the capacitance equal to
Because i=Q/t and the voltage across
the capacitor is
Because Q=CV. If initial voltage (t=0) on C is denoted VC
Now the output voltage VO=-VC(t)
In terms of the voltage
Thus the circuit provides an output voltage that is proportional to time
integral of the input.
We know the current I is the rate of change of charge
i=dQ/dt, also Q=CV
Since A is a virtual ground
the easiest is using the principle of superposition and virtual short concept.
To apply superposition we first reduce VI2=0
Which is clearly that of a difference amplifier
with a gain of R2/R1
above equation difference amplifier?
Basic principle of the switched-capacitor filter technique. difference amplifier?(a) Active-RC integrator. (b) Switched-capacitor integrator. (c) Two-phase clock (nonoverlapping). (d) During f1, C1 charges up to the current value of vi and then, during f2, discharges into C2.
ii) non- sinusoidal (or relaxation) oscillators-they produce an output which has square, rectangular or sawtooth wave form, employ circuit building blocks known as multivibrators.
oscillations following four ways: