1 / 10

R. Kluit Electronics Department Nikhef, Amsterdam.

Integrated Circuit Design. R. Kluit Electronics Department Nikhef, Amsterdam. 19/12/2008. IC design @Nikhef, R. Kluit. 2. ASIC application’s. 2004. 2 IC’s: 0.25 µ CMOS 3 prototypes 9/2000 => prod 3/2004 1400 PCB’s, 1000+4500 IC’s (prod. $43k)

vine
Download Presentation

R. Kluit Electronics Department Nikhef, Amsterdam.

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Integrated Circuit Design R. Kluit Electronics Department Nikhef, Amsterdam.

  2. 19/12/2008 IC design @Nikhef, R. Kluit 2

  3. ASIC application’s 2004 • 2 IC’s: 0.25µ CMOS • 3 prototypes • 9/2000 => prod 3/2004 • 1400 PCB’s, 1000+4500 IC’s (prod. $43k) • Chip-on-board;cleaning & bonding @ Nikhef • ++ Radiation & Area V. Gromov, P. Timmer, J-D Schipper, R. Kluit 19/12/2008 IC design @Nikhef, R. Kluit 3

  4. Most recent Designs • Design in Collaborations: • Si-strip detector front-end (0.25µm)Analog readout & Comparator • Contribution to new ATLAS Pixel FE chip • Design Internal: • IC’s for ALICE (0.25µm) • Bandgap reference (130nm) • GOSSIP frontend prototype’s (130nm) • Km3Net PMT front-end (0.35µm) 19/12/2008 IC design @Nikhef, R. Kluit 4

  5. CMOS IC technology • Design issues: • RregVt, 0Vt, HighVt, LowVt transistors • Radiation tolerance (design) • Technology Design rules • Process variations & matching • ESD • Rules for Manufacturability Bulk CMOS 19/12/2008 IC design @Nikhef, R. Kluit 5

  6. radiation tolerant ! ???? Bulk CMOS SOI Strained silicon Vdd 1.8-2.5V Vdd 1.2-1.5V Vdd 1-1.2V Vdd 1V Vdd 0.9-1V 6 Al 6 Cu 7 Cu 8 Cu 9 Cu Present Technologies feature size:Mass prod. start: Power & gate density scale relative to feature size scaling (x0.7). Vsupply Nr. metal layers 19/12/2008 IC design @Nikhef, R. Kluit 6

  7. “Features” of new Techn. • Random Dopant Fluctuations (RDF):@45nm; ~100 atoms channel length, 1000 dopants in channel • Variations in strain & Gate oxide thickness (~ 5 atoms @45nm) • Line Edge effects: R of connectivity • Solutions in Foundry & Design techniques;Global process variations of 45nm improved w.r.t. 90nm & 65nm ! 19/12/2008 IC design @Nikhef, R. Kluit 7

  8. Design Tools • Euro Practice Cadence platform: • Cadence:design entry & layout + analog & digital simulation. • Assura: Simulation & Verification • Mentor: Calibre for DRC & extraction (Ver.) • Synopsys: Logic Simulation, Digital Synthesis, Clock tree generation, Place & Route. • Software via Educational programs; affordable (€) BUT maintenance ¼ fte. 19/12/2008 IC design @Nikhef, R. Kluit 8

  9. ET Design expertise • Technologies: • Commercial CMOS • AMS 0.35µ:Design-Kit + Lib. • IBM 0.25µPDK + Lib. • IBM 0.13µ:PDK + Arm/IBM Lib. • People & Expertise : • (Electronics department) • 2+2 Designers have the skills for IC design. • Analog front-ends; device level circuit design • Digital design; control blocks & architectureVerilog => synthesis => routing. 19/12/2008 IC design @Nikhef, R. Kluit 9

  10. Present Technologies (2) ~0.7 ~0.7-2 ~0.72 ~0.7-2 • Transition to SOI, Vdd to ~1V • Radiation tolerance: increasing up to 90nm. Beyond ??? 19/12/2008 IC design @Nikhef, R. Kluit 10

More Related