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GLAST Large Area Telescope: Instrument Front-End Data Simulator (Isim) Dave Lauben

Gamma-ray Large Area Space Telescope. GLAST Large Area Telescope: Instrument Front-End Data Simulator (Isim) Dave Lauben dave.lauben@stanford.edu. Isim Concept and Constraints. What: Feed full-rate, realistic event data into 16 TEMs (EM2) Bank of COTS pattern generators too cumbersome

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GLAST Large Area Telescope: Instrument Front-End Data Simulator (Isim) Dave Lauben

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  1. Gamma-ray Large Area Space Telescope GLAST Large Area Telescope: Instrument Front-End Data Simulator (Isim) Dave Lauben dave.lauben@stanford.edu

  2. Isim Concept and Constraints • What: Feed full-rate, realistic event data into 16 TEMs (EM2) • Bank of COTS pattern generators too cumbersome • Why: Support development/verification of flight software • Fsw running on Daq needs realistic Glastsim events • Must guage efficiency/purity vs. Cpu power (g/J) • Must observe/control Daq deadtime pattern • How: Must deliver incredible performance at ZERO cost • Solution: Fpga on PCI cards in standard desktop PCs • Leverage recent technology for realtime digital video

  3. . . . . . . . . . Dwell time Fast-Or Pattern Strip address list, ToT, etc. Dwell time Null Null Dwell Dwell Null Noise Null Null Dwell time Fast-Or Pattern Strip address list, ToT, etc. 18x2x2 Treqs Isim Card Architecture (Tracker) Event Data Hopper F/E Cmd Log L1t/Tack Timestamp Log Isim GxRC Emulation Rate scale 4-Deep Fifo Strip Addr, Evt N+3 Multi-Tower Sync Timer Strip Addr, Evt N+2 Strip Addr, Evt N+1 } Strip Addr, Evt N LVDS LVDS Isim PCI Card 8 Cable bitstream Cmd passthru L1t/TAck Read Tokens TEM Cmd Decode Tokens, Readout COM GLT COM Coinc Logic Commands Event Data

  4. { 1. Data Prep { 2. Isim H/W & console { 3. EM-1, -2 Daq/Fsw Isim Near-term Fsw Development Support

  5. Replay unfiltered flight event data to hone onboard fsw L2/L3 filters Online and I&T/Calibration practice contention protocol Instrument command pre-upload verification 4 5 2 1 3 Diagnose in-flight faults Evaluate Daq effect on science (e.g. deadtime) No! X Isim Long-term Instr Ops Training/Support Note: “Flight” interface is here!

  6. Peak sustained data flow = ? Solar flare? 20 kHz Nominal sustained dataflow=? 10 kHz 1 kHz trigger rate 1 Hz 1-shot sustained duration 1-shot Fill SSR Converge histograms Swamp EB Fill Tem fifo Swamp EPU Full Orbit? Isim Primary Requirements Category • 1. Sustained event flow capacity: • a) Isim runs no matter what! • b) oversize event capacity? • c) tolerable event recycle? • 2. Multi-Tower Event Synchronicity • a) amongst Isim modules! • b) with installed towers? 3. Command Logging:Isim does simple write-to-file on Host of TEM commands received. 4. Event Rate Control:Isim scales relative Poisson intervals embedded in disk data? Live? 5. L1t (TACK) Logging:Isim logs which events were selected by L1t? 6. Command Response:Isim alters source data (switch file) upon receipt of TEM command? 7. Fault Detection/Action:Isim input fifo starved, Isim de-sync, TEM protocol error?

  7. Isim Appendix: Soyo Dragon $150 M-board Isim Cpu Parts List: Mainboard $150 AMD 1.6G $150 256M DDR $100 80G Disk $200 Encl+misc $100 subtotal $700* 2 cards/m-board: x16 Tkr/Cal +Acd 17-total $12k* Or if we’re lucky... 4 cards/m-board: x8 2xTkr/Cal+Acd 9-total $6.3k* *excludes PCB fab

  8. 2) Optional: Add front/end noise, config. emulation by Cpu w/ 266-533 MB/s N-S link (>6x margin) 1) Basic Isim: Req’s 40 of 132 MB/s (>3x margin). Data moves straight thru South bridge (Dma)! SiS 645 (Pentium-4) Via KT333 (AMD XP) Isim Appendix: Recent P4/AMD Chipsets While any 33 MHz PCI v2.2 with an ATA/66 disk can support the required 40 MB/s Isim dataflow, new chipsets now on the market will very likely permit on-the-fly data manipulation by the Cpu, allowing the Isim to emulate realtime response to front-end configuration changes, including: Tkr: Variable f/e threshold, one-shots, noisy strip masks, left/right readout direction Cal: True sparse data, Cal-Lo and Cal-Hi trigger thresholds, gain-mode change Acd: Veto threshold, one-shot width, and signal delay, true CNO threshold This is made possible by a memory bandwidth to the Cpu which is at least 2x the 133 MB/s PCI bandwidth, which itself is already 3x the basic requirement. Isim Card Disk data

  9. Isim Appendix: Recent Chipsets (AMD-XP) http://www.tomshardware.com/mainboard/02q1/020220/kt333-01.html

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