CS325 Instructions: Language of the Machine MIPS ARCHITECTURE - AN INTRODUCTION TO THE INSTRUCTION SET by N. Guydosh 2/2/04+. MIPS Approach.
shamt - shift amount - more laterfunct - function field - variations of the op code
Ex: lw $s1, 100($s2) # $s1 = memory($s2 + 100)
sw $s1,100($s2) # memory($s2 + 100) = $s1
Note: in MIPS all addresses are in units of bytes - thus if $s2 represents the 3rd
integer of an array of integers, then the offset in $s2 must be 2*4 = 8 and not 2…
remember addressing is origin 0 not 1, thus index is 2 not 3.
- how would a compiler translate the c statement?
a[i] = h + a[i]; ..... ? ... see p. 114assumptions:
$19 has the value 4*i
$18 is used for the variable h let astart be the symbolic value for the start of the array: lw $8, astart($19) # temp reg $8 gets a[i]
add $8, $18, $8 # temp reg $8 gets h + a[i]
sw $8, astart($19) # store h + a[i] back into a[i]
add immediate: addi
rt rs + imm # imm is a 16 bit integer constant
addi $1,$2,100 # $1 = $2 + 100
Set on less than immediate: slti
if (rs < imm) rt = 1; else rt = 0; # imm is a 16 bit integer constant
slti $s1,$s2,100 # if ($s2 < 100) $s1 =1; else $s1 = 0;
Set on less than: slt
if (rs < rt) rd = 1; else rd = 0;
slt $s1, $s2, $s3 #if $s2<$s3 $s1=1; else $s1=0;
slt is actually an R instruction but is closely related to the slti “I” instruction.
load upper immediate: lui
rt imm*216 # shift left 16 bits # imm is a 16 bit integer constant
lui $s1, 100 # rs unused (equal to 0)
# loads constant 100 to upper 16 bits of $s1, the lower half of s1 is set to zeros
see “control instructions in MIPS” for applications below
j imm # jump to target address
Unconditional jump to address designated by imm
32 bit address construction:
imm (26 bits) is concatenated to high 4 bits of the PC, and then
two zeros are appended to the low end to give a 32 bit address to
a word boundary.
… “extra range” is gained by interpreting the
resulting address as a word address … what is the analogous
situation in Intel addressing?
branch on not equal: bne reg1, reg2, targ_addrif (reg1 reg2) goto addr; #else fall throughTarget address is 16 bits
Absolute range is 0 - (216 -1) bytes
Q: How do we increase the range?
A: By adding the branch address to the pc register (program counter - contains the address of the current instruction) ... see p. 148
Interpret the immediate branch address as words and not bytes (another factor of 2). Range from PC is 218 bytes not words (p.150).
Assuming a 2’s complement representation of the immediate address, the range of the beq and bne would be ±215 words from the PC.
This is pc- relative addressing – the immediate address is relative to the pc: PC = PC + conditional branch address
NOTE: The ISA implies that the value of PC is actally PC+4 since it points to the next consecutive instruction to be executed. Thus PC = PCcurrent + 4 and the compiler will have to take this into account when generating the 16 bit offset for this instruction. See bottom pages 148 and 149, and pp. 347-350
This is similar to the short conditional jump in the Intel architecture
Q:How is a “branch on less than done (a “blt” instruction).
A: This instruction is too complicated to be natively implemented in this RISC architecture. It could appear as a pseudo-instruction to be translated to one or more native MIPS instructions. … Remember Amdahl’s Law
Here is how the “blt function” is done:
Use the slt instruction:
slt $t0, $reg1, $reg2 # $t0 gets a 1 if $reg1 < $reg2 ...
# type R instruction – see previous
bne $t0,$0, Less # GOTO Less IF $t0 0
#Note: $0 is a read only register containing a 0
jal address - type J
jr register - type RThe operand “address” in j and jal, is 26 bits,
maximum jump is 226words not bytes ==> 228 bytes
Only the lower 28 bits of the pc are replace for the j and j jump (upper 4bits are retained)and two zero bits are appended to the low end. ... see p. 150, 130
For jal, return address stored in $ra
Operation for address formation in j and jal
Byte-target-address = PC-hi-nibble||address||00
Note: the low two appended zeros are bits not nibbles
... used to implement the C language switch statementsee p. 129.
anywhere in memory
... See p. 129, 130, 133
stack or a “lifo” queue. this is implemented in software.
Caller saved or callee saved.
... see p. A-23 for mips register usage conventions
# swap is the callee - technically we need only to save registers
# $2 and $15, but this proc will save ‘em all ... See p. A-23# other register assignments :# $2 is the address of v[k]# local variable temp assigned to $15# register $16 used to store v[k+1]# register $29 is the stack pointer
# register $31 is the return address
swap: addi $29, $29,-12 # allocate stack space for 3 registers (12 bytes)# Callee saves registerssw $2, 0($29) # save $2 on the stack, $29 = $sp
sw $15, 4($29) # save $15 on the stack
sw $16, 8($29) # save $16 on the stack # Main guts of the program:muli $2, $5, 4 # reg $2 = k * 4 ... see later for muli add $2, $4, $2 # reg $2 = v(array base address) + k*4 # reg $2 now has the address of v[k] lw $15, 0($2) # reg $15 (temp) = v[k] lw $16, 4($2) # reg $16 = v[k+1] ... next element of v sw $16, 0($2) # v[k] = reg $16 = v[k+1] sw $15, 4($2) # v[k+1] = reg $15 = temp = v[k] # Callee restored registers:lw $2, 0($29) # restore $2 from stack, $sp is still as in 1st instruction lw $15, 4($29) # restore $15 from stack
lw $16, 8($29) # restore $16 from stack addi $29, $29, 12 # restore stack pointer# Procedure returnjr $31 # return to caller routine, call was not nested use $31=$ra
MIPS C code(Text, p. 149):
Machine Code (Text, p. 149):
Note: bne adds specifies branch destination relative to instruction 6 (the add instruction) rather than instruction 5 (bne itself).