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Frank Sill Torres and Davies W. de Lima Monteiro

Pipelined Successive Approximation Conversion (PSAC) with Error Correction for a CMOS Ophthalmic Sensor. Frank Sill Torres and Davies W. de Lima Monteiro Department of Electrical Engineering, Universidade Federal de Minas Gerais Natal, 02.09.2009. Focus / Main ideas

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Frank Sill Torres and Davies W. de Lima Monteiro

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  1. Pipelined Successive Approximation Conversion (PSAC) with Error Correction for a CMOS Ophthalmic Sensor Frank Sill Torres and Davies W. de Lima Monteiro Department of Electrical Engineering, Universidade Federal de Minas Gerais Natal, 02.09.2009

  2. Focus / Main ideas • Low power Analog Digital Converter (ADC) for ophthalmic applications • Error correction for ADC

  3. Schedule • Motivation • Preliminaries • Pipelined Successive Approximation Converter (PSAC) • Error Correction Techniques • Results • Conclusion

  4. Motivation Adaptive Optics Adaptive optics: Dynamic sensing and correction of wavefronts Wavefront: Hypothetical surface with equal phase

  5. Motivation Wavefront Detection CMOS chip: PSD matrix = X ADC = Y Position Detection Sensor (PSD) - Quad-cell / light spot

  6. Preliminaries Successive Approximation Converter • Generation of internal analog signal VD/Awith Digital Analog Converter (DAC) • Comparison of VD/A with input signal Vin • Modification of VD/A by bits D0D1..DN-1 until closest possible value to Vin Vref – reference voltage S&H – Sample and Hold circuit

  7. Preliminaries Pipelined Converter • Conversion separated in clocked stages • In each stage: subtraction of conversion result from stage input • Pipelined conversion of subsequent input signals

  8. Preliminaries Comparison / Ideas • Successive Approximation Converter (SAC) Low Power/ low area Slow • Pipelined Converter Fast High power / high area • Idea: • Combination of both concepts

  9. Pipelined Successive Approximation Converter Schematic

  10. Pipelined Successive Approximation Converter Schematic – Successive Approximation Converter

  11. Error Correction Techniques Parameter Variations • Sources: • Production variations • Supply, temperature variations • Wear-out, ESD, … • Main problems at PSAC: • Offset voltage variation • Wrong matching • Main affected components: • Comparator • Gain amplifier

  12. Error Correction Techniques Redundant Comparator • Wrong residue Vres voltage through comparator error • Residue error εres = multiple of SAC’s VLSB_SAC • IF absolute maximum comparator error < VLSB_SAC THENεres = [-VLSB_SAC,0,VLSB_SAC] • Input voltage Vin,i+1 for next SAC (after gain amplifier): • At comparator error: • Vin,i+1 < 0 (if εres = -VLSB_SAC) • Vin,i+1 > Vref (if εres = VLSB_SAC)

  13. Error Correction Techniques Redundant Comparator cont’d • Idea: • Error detection after multiplication • In case of error → Correction in multiplication stage (by adding or subtraction of VLSB_SAC) → Correction in digital stage • Advantages: • Error detection and error correction • Disadvantages • Additional clock cycle • Additional hardware

  14. Error Correction Techniques Foreground Calibration • Problem: nonlinearity of gain amplifier • Short conversion pauses (< 2 ms) allowed in desired application → foreground calibration possible • Voltage ramp for both amplifier → conversion by PSAC • Amplification error determination by linear regression algorithm • Calibration: • 1st : Last SAC (24 = 16 steps, voltage ramp accuracy = 8 VLSB) • 2nd: Middle SAC (27 = 128 steps, voltage ramp accuracy = 1 VLSB) • For all three possible signals with negative input

  15. Results Simulation Overview • Technology: AMS c35 (CMOS 0.35 um) • Vcc = 1.65 V, VSS = -1.65V • Step size = 0.2 mV • Monte Carlo simulations (models based on AMS library) • Frequency: 8 MHz (1 MSPS) • Power Dissipation: 8.2 mW

  16. Results Differential Non-Linearity (DNL) without Error Correction Max. DNL > 130 VLSB Max. INL > 600 VLSB INL – Integral Non-Linearity

  17. Results Differential Non-Linearity (DNL) with Error Correction Max. DNL = 0.7 VLSB Max. INL = 0.9 VLSB

  18. Conclusion • Combination of two ADC concepts by Pipelined Successive Approximation Converter (PSAC) • Low power and moderate speed • Effective error correction through redundant comparator and foreground calibration • Future Work: • Improvement of the gain amplifier • Combination with ophthalmic sensor

  19. Acknowledgements • This work was sponsored by: • CNPq • FAPEMIG • INCT-DISSE/CNPq • Thanks to: • OptMAlab crew • PPGEE / DEE / UFMG

  20. THANK YOU! contacts: franksill@ufmg.br davies@ufmg.br

  21. mirror surface Deformable MEMS Mirror top view

  22. Pipelined Successive Approximation Converter Schematic – Flow • Load - New analog input into the SAC • ZERO - Resetting of SAC’s output bits • SET Bx - Successive bit setting and result estimation • LAST-BIT - Estimation of result for last Bit (Bit n) • WAIT - Generation of input analog signal for the next stage (only 1st and 2nd SAC)

  23. Error Correction Techniques Redundant Comparator cont’d Dynamic Comparators Vin < 0 ? Vin > Vref? Switches for generation of signal ADD

  24. Error Correction Techniques Foreground Calibration - Principle Vin Desired behavior Real behavior Vout (from PSAC) Correction VPSAC (measured value) Linearized real behavior Vin (from ramp)

  25. Dynamic Comparator

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