Adaptive Instrument Module through Programmable Logic

1. Richard F. Conde, Ann Garrison Darrin, F. Charles Dumont The Johns Hopkins University Applied Physics Laboratory Dr. Neil Bergmann Dr. Anwar Dawood CRCSS - Queensland University of Technology Adaptive Instrument Module through Programmable Logic Phil Luers -NASA/GSFC Steve Jurczyk - NASA/LaRC

2. Motivation for Reconfigurable Processing in Space • Impossible to fix hardware design errors after launch • Improve algorithms after launch • Would like to re-use hardware design to reduce NRE spacecraft costs • High performance - reconfigurable processor offers hardware speed with software flexibilty • We are developing a prototype spaceborne reconfigurable processor called the Adaptive Instrument Module (AIM). • See poster by Bergmann and Dawood for expanded discussion on use of Reconfigurable Computers in space

3. Spacecraft use of Reprogrammable FPGAs • SRAM programmed FPGAs can be used as the basis of a reconfigurable processor • Challenges for effective use in spacecraft: • Configuration Memory Upsets: SRAM-based FPGAs are susceptible to radiation-induced upsets in configuration memory. The frequency of these upsets must be investigated, and techniques developed to detect and correct them. • Management of Multiple Configurations: Spacecraft have limited onboard resources and limited communications to ground stations. Techniques for managing the configuration data for FPGAs onboard a spacecraft will be very different than ground applications. These techniques need to be investigated, developed and analysed.

4. Partnerships and Roles HARDWARE • NASA - Needs and Requirements • Goddard Space Flight Center - Team Lead Phil Luers • LaRC - Team Lead Steve Jurczyk • The Johns Hopkins University APL - hardware design, fabrication, and test • Team Lead - Rich Conde SOFTWARE • Cooperative Research Center for Satellite Systems - Queensland University of Technology - software development, system design, flight opportunity, mission operations • Team Lead - Dr. Neil Bergmann

5. AIM Requirements • Implement a low cost, radiation tolerant, reconfigurable processor for Australian Fedsat and other spacecraft • Use Xilinx XQR4062 FPGA as the heart of the reconfigurable processor (available in a rad tolerant version) • Upload, store and manage multiple FPGA configurations • Detect, correct, and log single event upset induced configuration errors in the Xilinx FPGA • Run standalone reconfigurable computing experiments - not be dependent on another subsystem. Verify upload, management protocols & collect SEU data • Process instrument data with reconfigurable hardware - instrument data processed with algorithms loaded into FPGA

6. AIM Block Diagram 8 MByte Flash Memory (Configurations) 256 KByte EEPROM Memory (Code) 1 MByte SRAM Memory (Code/Data) RS-422 Spacecraft C&DH Interface 80C196 Microprocessor Data Bus +5V +28V Spacecraft Power Power Regulation Expanded Address Bus Memory Controller Readback Controller Data +3.3V Actel FPGA Configuration Readback Instrument Control Reconfigurable Computing Unit Xilinx XQR4062 Instrument Data 32 KByte SRAM Temperature & Voltage Status Spacecraft

7. FPGA Configuration & Readback Setup • Configurations loaded into flash memory from ground • Microprocessor loads selected configuration from flash memory into Xilinx Operation • Software activates readback from Xilinx • Readback controller continuously loads readback data into a pair of 128-bit ping-pong registers, processor reads one register while other being loaded • Takes ~1 second to readback entire configuration memory • Any errors are logged, and configuration will be reloaded

8. AIM Flight Unit Characteristics • Weight: estimated 1 kg • Size: 16 cm x 17.5 cm x 3.0 cm • Power: 2.5W (from +28V) • Parts selected for radiation tolerance and availability: • Xilinx XQR4062XL - 62,000 gate SRAM-based FPGA • UTMC UT80C196KD 16-bit microcontroller • SEI 28C010TRPFB-15 512Kx8 EEPROM • SEI 29F0408RP 4Mx8 Flash • Austin/Motorola 5C512K8F 512Kx8 SRAM • Actel A1280A fuse link FPGA

9. AIM Radiation Effects • All parts selected are immune to single event latchup, which can result in device destruction • Single Event Upset • Only concern is processor SRAM - can upset at rate of 3 upsets per device-day during solar max conditions (may switch to harder SRAM or add third SRAM chip for EDAC) • Actel FPGA designed using C-modules only • Total Dose • Softest parts are 512K x 8 SRAM and Actel FPGA, will use tantalum shielding to increase effective hardness to > 15 krads

10. AIM Flight Module Area Study 145 mm (5.65 in) 175 mm (6.83 in)

11. AIM Status • Breadboard designed, fabricated, checked out • 80C196 running with software development tools • Sample Xilinx configuration loaded into Flash Memory • Software being developed with IAR Embedded Workbench • About to start layout and packaging of flight board • Scheduled for launch in November 2000

12. AIM Breadboard

13. Lessons Learned (so far) • Xilinx readback restrictions - must occur between 1 Mbit/s and 2 Mbit/s • Avoid ringing on write signal used to load configuration data into Xilinx - can get configuration errors • Xilinx turn-on current surge

14. Next Step • There will be an ongoing need to use Rad-Tolerant SRAM-configured FPGAs even when Rad-Hard SRAM-configured FPGAs become available due to higher gate count in the Rad-Tolerant devices • Use results from AIM to design a general purpose “drop-in” module using Rad-Tolerant FPGA for both reconfigurable processing and general digital logic applications • One Solution - a module that contains configuration and auto-checking hardware needed for operation without requiring continuous processor servicing • Host processor loads configuration and then the module takes care of readback, error checking, and configuration reload

15. Module for Spaceflight Applications Xilinx FPGA (Reconfigurable Processor) Application Input Application Output Configuration Readback Host Processor provides configuration, receives flag if error detected and corrected FlashMemory (Configurations) Actel FPGA (Controller)

16. Future Space Applications The AIM has the potential for: • Leading to a card with a generic interface for instrument applications - more practical than previous attempts because can tailor hardware in addition to software • Adapting to changing science collection needs - improved algorithms, changed data rates • Reducing satellite costs by re-using generic AIM hardware

17. Thank You • With acknowledgements to current and future sponsors and advocates……. • LaRC: Steve Jurczyk • GSFC: Phil Luers • Next Generation Space Telescope NGST - Joe Burt • Solar Terrestrial Probes STP - Abby Harper • New Millennium Program NMP - Fuk Li • NASA HQ - Dr. Dana Brewer