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Advanced Digital Logic Design Using Verilog, State Machines, and Synthesis for FPGAs

2012-05-27. "Computer Design" by Sunggu Lee. 2. Syllabus. Digital Logic ReviewCombinational

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Advanced Digital Logic Design Using Verilog, State Machines, and Synthesis for FPGAs

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    1. Advanced Digital Logic Design Using Verilog, State Machines, and Synthesis for FPGAs Sunggu Lee

    2. 2012-05-28 "Computer Design" by Sunggu Lee 2 Syllabus Digital Logic Review Combinational & Sequential Circuit Design Review HDL-Based Design Design and Synthesis using Verilog HDL (Hardware Description Language) State Machine Design Introduction to FPGAs Design Examples Liquid Crystal Display (LCD) Interface Universal Serial Bus (USB) Interface Pipelined Multiply-Accumulate (MAC) Unit Computer Design Datapath, Control, Memory, Integration, Pipelining

    3. 2012-05-28 "Computer Design" by Sunggu Lee 3 Chapter 1: Digital Logic Review Digital Logic Circuits Manipulate digital (discrete-valued) signals Digital Signal Representation Uses binary number system Bit, byte, word, nibble Manipulation of bit values (0, 1) Based on a mathematical theory of logic (false, true) Arithmetic (and even automated control operations) can be performed based on logic operations

    4. 2012-05-28 "Computer Design" by Sunggu Lee 4 Binary value representation in electronic circuits Can use voltage, current, transition, frequency, etc. E.g., LSTTL (transistor-transistor logic) chips for inputs, ‘0’ = 0.0-0.8V and ‘1’ = 2.0-5.0V; for outputs, ‘0’ = 0.0-0.5V and ‘1’ = 2.7-5.0V Reason for different ranges, intermediate voltage interpretation? Binary Codes Meaning of a sequence of binary bits (e.g., 11001111) unsigned integer, character, floating-point number, part of a binary program, part of a video or audio stream, etc. Interpreting binary bits as an unsigned number radix r numbers (radix-10, radix-2, radix-16, etc.) qp-1 qp-2 ... q0 . q-1 q-2 ... q-n = Si=-np-1 qi * ri need to practice fast conversions: decimal, hex, binary Signed numbers 1’s complement: negative -> invert every bit 2’s complement: negative -> invert every bit, add 1 to “lsb”

    5. 2012-05-28 "Computer Design" by Sunggu Lee 5 Examples Assume 8-bit words (p = 8, n = 0). 1’s complement: 11001011 = ( ? )10 2’s complement: 11001011 = ( ? )10 Let A = ( 67 )10 = ( ? ) in 2’s complement Let B = ( -128 )10 = ( ? ) in 2’s complement perform A + B, A - B using two 2’s complement numbers Is there anything strange? Other codes BCD (binary coded decimal): 0011 1001 0101 = ( ? )10 excess-k: e.g., excess-3, excess-127, etc. Gray code: e.g., 00, 01, 11, 10 parity (even parity, odd parity): 101001010100 --> parity bit = ? with even parity 010100010111 --> parity bit = ? with odd parity

    6. 2012-05-28 "Computer Design" by Sunggu Lee 6 Digital Logic Theory Boolean Algebra (uses n-valued variables) Switching Algebra (special case of Boolean Alg.) Defined on the sextuple [ S, * , + , ‘ , 0 , 1 ] S : set of elements (variables) * , + , ‘ : set of operators 0, 1 : elementary values Basic axioms: 0 + 0 = 0, A + 0 = A, etc. Basic theorems: Tables 1.2 and 1.3 of [Lee 2000] Absorption (T9): A + A * B = A; (T9’): A * (A + B) = A Consensus (T12): XY + X’Z + YZ = XY + X’Z; dual = ? DeMorgan’s: (x + y)’ = x’y’; (xy)’ = x’ + y’ Generalized DeMorgan’s: [ f (x1, x2, …, xn, 0, 1, +, * ) ]’ = f (x1’, x2’, …, xn’, 1, 0, *, + ) Principle of Duality: interchange (+, *) and (0, 1)

    7. 2012-05-28 "Computer Design" by Sunggu Lee 7 Hardware Implementations SSI-Level Logic Gates AND, OR, inverter, NAND, NOR CMOS implementations Other SSI Gates XOR, XNOR, buffer, tri-state buffer, wired-AND MSI Devices MUX, DEMUX, Decoder, Encoder, Priority Encoder, Adder, Buffer, Comparator, Parity Generator, Parity Checker, … NAND-gate Logic Implementations Any switching expression can be formed using NANDs The NAND is a _________ gate? Multiplexer(MUX)-based Logic Implementations

    8. 2012-05-28 "Computer Design" by Sunggu Lee 8 Logic Gate Implementations Functionally Complete Set of Gates {OR, AND, NOT} ? { + , * , ‘ } { + , ‘ } { * , ‘ } Universal Gate NAND Similarly for NOR

    9. 2012-05-28 "Computer Design" by Sunggu Lee 9 Conversion to NAND-Gate Circuits

    10. 2012-05-28 "Computer Design" by Sunggu Lee 10 2-1 MUX Gate Implementation AND-OR implementation Tri-state buffer implementation

    11. 2012-05-28 "Computer Design" by Sunggu Lee 11 Using a MUX as a Universal Logic Device Any function of k variables can be implemented with a 2k-1 (2k-to-1)MUX Any function of (k+1) variables can be implemented with a 2k-1 (2k-to-1) MUX Use the (k+1)’th variable, in complemented or noncomplemented form, as a possible input Similar to a variable-entered K-map

    12. 2012-05-28 "Computer Design" by Sunggu Lee 12 Using a Decoder and NAND Gates Any function of k variables can be implemented using a k-2k decoder and NANDs

    13. 2012-05-28 "Computer Design" by Sunggu Lee 13

    14. 2012-05-28 "Computer Design" by Sunggu Lee 14 Combinational Logic Minimization Meaning Which is simpler: f = ace’ + bc, g = (a + b + d)e’ ? Karnaugh Map: Used to produce minimal SOP or POS Minimize F = A’B + A’C + A’D + ACD F = A’B (C’D’ + C’D + CD’ + CD) + A’C (B’D’ + B’D + BD’ + BD) + A’D (B’C’ + B’C + BC’ + BC) + ACD (B’ + B) = A’BC’D’ + A’BC’D + A’BCD’ + A’BCD + … --> canonical sum-of-products (SOP) form Draw K-map and then solve Result should be F = CD + A’B + A’C + A’D (1) (2) (3) (4)

    15. 2012-05-28 "Computer Design" by Sunggu Lee 15

    16. 2012-05-28 "Computer Design" by Sunggu Lee 16 K-Maps

    17. 2012-05-28 "Computer Design" by Sunggu Lee 17

    18. 2012-05-28 "Computer Design" by Sunggu Lee 18 Quine-McCluskey (Q-M) Method Preliminary Concepts Minterm Ex: f1(w,x,y,z) = S (0, 1, 8, 9) Literal = w’x’y’z’ + w’x’y’z + … Implicant = w’x’y’ + wx’y’ Prime Implicant (PI): A PI p of F is an implicant of F such that the deletion of any literal from p results in a product term which is NOT an implicant of F. A “largest possible” implicant is a PI An essential PI (EPI) of F is a PI that contains a minterm not covered by any other PI Non-essential PIs (NEPI): {NEPI} = {PI} - {EPI}

    19. 2012-05-28 "Computer Design" by Sunggu Lee 19 Sum-of-Products (SOP) Minimization must include all EPI’s and perhaps a few NEPI’s Q-M Method A systematic tabular method for generating the EPI’s and NEPI’s Step 1: Find the PI’s Step 2: Find the EPI’s Step 3: Find the smallest collection of NEPI’s that cover the “remaining” minterms Identify minterms, literals, PI’s, EPI’s and NEPI’s Example problem (a K-map can be used): f = S (1, 3, 6, 8, 9, 12, 13, 18, 19, 20, 21, 24, 25, 27, 28, 29)

    20. 2012-05-28 "Computer Design" by Sunggu Lee 20 Sequential Circuit Design Block Diagram for a General Sequential Circuit

    21. 2012-05-28 "Computer Design" by Sunggu Lee 21 Types of Sequential Circuits Asynchronous sequential State is permitted to change at any time Synchronous sequential State is permitted to change only at times specified by a clock signal Memory Devices Asynchronous sequential circuits Delay element, wire delay, latch, flip-flop Synchronous sequential circuits Latch: level-triggered device (typical usage) Flip-Flop: edge-triggered device (typical usage)

    22. 2012-05-28 "Computer Design" by Sunggu Lee 22 Basic R-S Latch Design

    23. 2012-05-28 "Computer Design" by Sunggu Lee 23 Enabled R-S Latch Design

    24. 2012-05-28 "Computer Design" by Sunggu Lee 24 D-Latch Design

    25. 2012-05-28 "Computer Design" by Sunggu Lee 25 D Flip-Flop, Master-Slave Device

    26. 2012-05-28 "Computer Design" by Sunggu Lee 26 J-K Flip-Flop

    27. 2012-05-28 "Computer Design" by Sunggu Lee 27 Synchronous Sequential Circuit Design Typically based on Finite State Machines (FSMs) Mealy machine Outputs depend on the present inputs and the current state Moore machine Outputs depend on the current state only FSM Design Steps (1) Draw a state diagram (or state table) (2) Make a state assignment (3) Derive a state transition table (4) Derive logic equations (5) Derive logic diagram from the logic equations

    28. 2012-05-28 "Computer Design" by Sunggu Lee 28 Counter Example (Prob. 2-16) 3-bit synchronous binary counter using D FF’s Step (1): State Diagram

    29. 2012-05-28 "Computer Design" by Sunggu Lee 29 Step (2): State Assignment Use variables (A,B,C) and 3-bit binary assignment Step (3): State Transition Table

    30. 2012-05-28 "Computer Design" by Sunggu Lee 30 Step (4): Derivation of Next State Equations

    31. 2012-05-28 "Computer Design" by Sunggu Lee 31 Step (5): Logic Diagram

    32. 2012-05-28 "Computer Design" by Sunggu Lee 32 Sequence Detector (Prob. 2-22) Design sequence detector (for 1101) using J-K FF Step (1): State Diagram

    33. 2012-05-28 "Computer Design" by Sunggu Lee 33 Steps (2) and (3): State Assignment & State Transition Table

    34. 2012-05-28 "Computer Design" by Sunggu Lee 34 Step (4): Derivation of Next State and Output Equations

    35. 2012-05-28 "Computer Design" by Sunggu Lee 35 Step (5): Logic Diagram

    36. 2012-05-28 "Computer Design" by Sunggu Lee 36 Sequential MSI Devices n-bit Register Shift Register

    37. 2012-05-28 "Computer Design" by Sunggu Lee 37 Universal Shift Register Binary Ripple Counter

    38. 2012-05-28 "Computer Design" by Sunggu Lee 38 Hazards (due to Races)

    39. 2012-05-28 "Computer Design" by Sunggu Lee 39 Elimination of Hazards

    40. 2012-05-28 "Computer Design" by Sunggu Lee 40 Metastability Metastable signals can occur due to unstable data values during clock signal transitions Ex:

    41. 2012-05-28 "Computer Design" by Sunggu Lee 41 Solutions to Metastability Metastability can never be completely eliminated Try to reduce the likelihood of metastable values Possible solutions for asynchronous data inputs Use data inputs with extremely fast transitions Buffer data through a series of inverters before using them Buffer data through several flip-flops before using them

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