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ELEN 468 Advanced Logic Design

ELEN 468 Advanced Logic Design. Lecture 23 Testing. Verifies correctness of design Performed by simulation, hardware emulation, or formal methods Performed prior to manufacturing. Verifies correctness of manufactured hardware Two-part process:

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ELEN 468 Advanced Logic Design

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  1. ELEN 468Advanced Logic Design Lecture 23 Testing ELEN 468 Lecture 23

  2. Verifies correctness of design Performed by simulation, hardware emulation, or formal methods Performed prior to manufacturing Verifies correctness of manufactured hardware Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware Test application performed on every manufactured device Verification vs. Testing ELEN 468 Lecture 23

  3. Why Do We Need Testing? • Properly designed chip may fail in field • Transient failures – under heating, radiation … • Intermittent failures – random, finite duration • Permanent failures • Manufacturing defects • Wafer defects • Contaminated atmosphere in clean room, dust … • Impure processing gasses, water, chemicals … • Photomask misalignment ELEN 468 Lecture 23

  4. Testing Levels and Implied Cost • Wafer: 0.01 – 0.1 • Packaged-chip: 0.1 – 1 • Board: 1 – 10 • System: 10 – 100 • Field: 100 – 1000 ELEN 468 Lecture 23

  5. Types of Defects • Wire shorts • Discontinuous wires, may due to stress or peeling • High resistance vias • Gate to source/drain junction short • Threshold voltage change ELEN 468 Lecture 23

  6. Fault Models • Why model faults? • I/O function tests inadequate, real defects too numerous and often not analyzable • A fault model • Identifies targets for testing • Makes analysis possible • Common fault models • Transistor open and short faults • Single stuck-at faults ELEN 468 Lecture 23

  7. Single Stuck-at Fault • Three properties define a single stuck-at fault • Only one line is faulty • The faulty line is permanently set to 0 or 1 • The fault can be at an input or output of a gate • Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults Faulty circuit value Good circuit value j c 0(1) s-a-0 d a 1(0) g h 1 z i 0 1 e b 1 k f Test vector for h s-a-0 fault ELEN 468 Lecture 23

  8. Fault Equivalence and Collapsing • Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2 • Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. ELEN 468 Lecture 23

  9. Equivalence Rules sa0 sa0 sa1 sa1 sa0 sa1 sa0 sa1 WIRE sa0 sa1 sa0 sa1 AND OR sa0 sa1 sa0 sa1 sa0 sa1 NOT sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 NAND NOR sa1 sa0 sa0 sa1 sa0 sa1 sa1 sa0 sa1 FANOUT ELEN 468 Lecture 23

  10. Checkpoints • Primary inputs and fanout branches of a combinational circuit are called checkpoints • Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit. Total fault sites = 16 Checkpoints ( ) = 10 ELEN 468 Lecture 23

  11. Transistor (Switch) Faults • MOS transistor is considered an ideal switch and two types of faults are modeled: • Stuck-open -- a single transistor is permanently stuck in the open state • Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage • Detection of a stuck-open fault requires two vectors • Detection of a stuck-short fault requires the measurement of quiescent current (IDDQ) ELEN 468 Lecture 23

  12. Stuck-Open Example Vector 1: test for A s-a-0 (Initialization vector) Vector 2: (test for A s-a-1) VDD PMOS A two-vector stuck-open test can be constructed by ordering two stuck-at tests A 0 0 1 0 Stuck-open B C 0 1(Z) Good circuit states NMOS Faulty circuit states ELEN 468 Lecture 23

  13. Stuck-Short Example Test vector for A s-a-0 VDD A 1 0 Stuck-short IDDQ path in faulty circuit B Good circuit state C 0 (X) Faulty circuit state ELEN 468 Lecture 23

  14. Testing Techniques • IDDQ test – detect short circuit current • Test pattern generation and verify output ELEN 468 Lecture 23

  15. Test Pattern for Stuck-At Faults a b Ygood = a●b●c c SA1 a Ya-SA1 = b●c No need to enumerate all input combinations to detect a fault b c Test pattern: {a,b,c} = 011 ELEN 468 Lecture 23

  16. Path Justification and Sensitization Justification Test SA0 ‘1’ ‘1’ Sensitization ELEN 468 Lecture 23

  17. Automatic Test Pattern Generation (ATPG) • Functional ATPG – generate complete set of tests for circuit input-output combinations • 129 inputs, 65 outputs: • 2129 = 680,564,733,841,876,926,926,749, 214,863,536,422,912 patterns • Using 1 GHz ATE, would take 2.15 x 1022 years • Structural test: • No redundant adder hardware, 64 bit slices • Each with 27 faults (using fault equivalence) • At most 64 x 27 = 1728 faults (tests) • Takes 0.000001728 s on 1 GHz ATE • Designer gives small set of functional tests – augment with structural tests to boost coverage to 98+ % ELEN 468 Lecture 23

  18. D-Logic Inverter • D • 1 in good • 0 in fault • D’ • 0 in good • 1 in fault • X – don’t care ELEN 468 Lecture 23

  19. D-Algorithm ‘1’ Monitor output in D logic ‘1’ Test SA0 = trace back input to enable D ELEN 468 Lecture 23

  20. Algorithm Speedups Algorithm D-ALG PODEM FAN TOPS SOCRATES Waicukauski et al. EST TRAN Recursive learning Tafertshofer et al. Est. speedup over D-ALG (normalized to D-ALG time) 1 7 23 292 1574 ATPG System 2189 ATPG System 8765 ATPG System 3005 ATPG System 485 25057 Year 1966 1981 1983 1987 1988 1990 1991 1993 1995 1997 ELEN 468 Lecture 23

  21. Fault Simulation • Fault simulation Problem • Given • A circuit • A sequence of test vectors • A fault model • Determine • Fault coverage - fraction (or percentage) of modeled faults detected by test vectors • Set of undetected faults • Motivation • Determine test quality and in turn product quality • Find undetected fault targets to improve tests ELEN 468 Lecture 23

  22. Fault Coverage and Defect Level • W = 1 – Y(1-T) • W: probability of shipping a defective part • Y: manufacturing yield • T: fault coverage ELEN 468 Lecture 23

  23. Fault Simulator in a VLSI Design Process Verification input stimuli Verified design netlist Fault simulator Test vectors Modeled fault list Test compactor Remove tested faults Delete vectors Low Fault coverage ? Test generator Add vectors Adequate Stop ELEN 468 Lecture 23

  24. Fault Simulation Scenario • Mostly single stuck-at faults • Sometimes stuck-open, transition, and path-delay faults • Equivalence fault collapsing of single stuck-at faults • Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis • Fault sampling -- a random sample of faults is simulated when the circuit is large ELEN 468 Lecture 23

  25. Fault Simulation Algorithms • Serial • Parallel • Concurrent • Probabilistic ELEN 468 Lecture 23

  26. Serial Algorithm • Algorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault: • Modify netlist by injecting one fault • Simulate modified netlist, vector by vector, comparing responses with saved responses • If response differs, report fault detection and suspend simulation of remaining vectors • Advantages: • Easy to implement, less memory • Most faults, including analog faults, can be simulated • Disadvantage: • Much repeated computation, CPU time prohibitive for VLSI circuits ELEN 468 Lecture 23

  27. Parallel Fault Simulation • Best with two-states (0,1) • Exploits inherent bit-parallelism of logic operations on computer words • Multi-pass simulation: each pass simulates w-1 new faults, where w is the machine word length • Speed up over serial method ~ w-1 • Not suitable for circuits with timing-critical and non-Boolean logic ELEN 468 Lecture 23

  28. Parallel Fault Simulation Example Bit 0: fault-free circuit Bit 1: circuit with c s-a-0 Bit 2: circuit with f s-a-1 1 1 1 a c s-a-0 detected 1 0 1 1 0 1 1 1 1 e 1 0 1 c b s-a-0 g 0 0 0 d s-a-1 f 0 0 1 ELEN 468 Lecture 23

  29. Concurrent Fault Simulation • Event-driven simulation of fault-free circuit • Only note those parts of the faulty circuit that differ in signal states from the fault-free circuit • A list per gate containing copies of the gate from all faulty circuits in which this gate differs • List element contains fault ID, gate input and output values • Faster than parallel simulation • Uses most memory ELEN 468 Lecture 23

  30. 0 0 0 0 0 0 1 0 0 1 0 0 Concurrent Fault Simulation Example a0 c0 e0 b0 0 1 1 1 0 0 0 0 0 0 1 1 1 a 1 1 1 1 b e 1 1 1 c g 1 0 0 1 0 e0 a0 c0 b0 f d b0 d0 f1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 g0 1 d0 f1 ELEN 468 Lecture 23

  31. Probabilistic Fault Simulation • Identify test vectors with high toggle coverage • Use them as basis for test vectors • Correlation: toggle coverage  fault coverage • Toggle tests are simpler ELEN 468 Lecture 23

  32. Fault Sampling • A randomly selected subset (sample) of faults is simulated • Measured coverage in the sample is used to estimate fault coverage in the entire circuit. • Advantage: saving in computing resources (CPU time and memory) • Disadvantage: limited data on undetected faults - hard to identify location of coverage problems ELEN 468 Lecture 23

  33. Delay Fault Testing • Half open circuit • Half short circuit • Functionality is not affected • Timing performance is degraded ELEN 468 Lecture 23

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