Chapter 6 Classic Design. 6.1 Introduction. Figure 6.1 Typical CCS. Figure 6.2 Simplified CCS framework. There are two kinds of design methods for the design of CCS, i.e., indirect design method and direct design method. 6.2 Indirect design method. Discretize.
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Chapter 6
Classic Design
Figure 6.1 Typical CCS
Figure 6.2 Simplified CCS framework
There are two kinds of design methods for the design of CCS, i.e., indirect design method and direct design method.
Discretize
Figure 6.3 Indirect design method
Advantage:
Simple; Abundant experience in continuous design
Disadvantage:
Have a larger phase delay than that of continuoustime system
Concrete procedure:
1.Choose sampling period, and design preantialiasing filter
2.Design or discretize continuous controller
3.Test the performance of the discrete system
4. If the system cannot meet the specification, there are three ways to improve it.
a. Choose the more appropriate discretized method
b. Increase sampling frequency
c. Modify the original continuous controller
6.2.1 Approximations based on transfer functions
The system’s transfer function
is equivalent to the differential
equation
(6.1)
where a=1/(RC)
Figure 6.4 Continuous time filter
1.Numerical integration
Figure 6.5 Sketches of three ways the area under the curve from
kT to kT+T can be approximated
(1) forward rectangular rule (also known as Euler’s rule)
(2) backward rectangular rule
(3) trapezoid rule
(4) Frequency prewarping
set
Then
If is small ; ,
Example 6.1
2.Input response invarianceStep invariance
H(z) = (1 – z1) Z{G(s)/s}
gives an appropriate pulsetransfer function H(z) for a given transfer function G(s).
Remarks:
1. Stable obtain stable
2. Frequency folding phenomena, but thanks to the lowpass
characteristics of the ZOH, it is a little better.
3. Complex computation for largescale systems
4. Steadystate value is invariant, i.e., G(s)s=0=H(z)z=1
6.2 Indirect design method
Example:
bode(1,[1 1])
hold on
dbode([1 1],[3 1],1)
6.2 Indirect design method
Example:
sysc=tf([1 1 9],[1 2 9]);
sysdt=c2d(sysc,1,'tustin')
Transfer function:
0.8824 z^2 + 0.5882 z + 0.6471

z^2 + 0.5882 z + 0.5294
Sampling time: 1
>> bode(sysc)
>> hold on
>> dbode([0.8824 .5882 .6471],[1 .5882 .5294],1)
6.2 Indirect design method
Example:
sysc=tf([1 1 9],[1 2 9]);
sysdp=c2d(sysc,1,'prewarp',3)
Transfer function:
0.9775 z^2 + 1.891 z + 0.9326

z^2 + 1.891 z + 0.9101
Sampling time: 1
>> dbode([.9775 1.891 .9326],[1 1.891 .9101],1)
>> bode(sysc)
>> hold on
>> dbode([0.8824 .5882 .6471],[1 .5882 .5294],1)
6.2 Indirect design method
Comparison of discretization methods
6.2.2 Approximations based on state models
(1) Forward rectangular rule is to replace s with (z1)/T
is a statespace formula for the forward rule equivalent.
(2) For the backward rule, substitute with the result
which corresponds to the time domain equation
(3) Finally, for the trapezoid or bilinear rule, the ztransform equivalent is obtained
where , , and J are given as follows:
6.2.3 Digital PID controllers
(1) Analog PID controllers
e
1
t
t0
u
Kp
u0
t0
t
e
1
t
t0
Kp
u
Kp
u0
Ti
t0
t
e
1
t0
t
Kp
u
Kp
u0
Ti
t0
t
(2) Digital PID controllers
Suppose t= kT, k= 0,1,2,…
So e(t) = e(kT)
We call it position algorithm or an absolute algorithm.
The output of the controller is the absolute value of the control signal, for instance, a valve position.
we call it incremental algorithm.
or
6.2 Indirect design method
In an incremental algorithm, the output of the controller should
then represent the increments of the control signal.
which is equivalent to the following equation
6.2 Indirect design method
P control
PI control
PD control
6.2 Indirect design method
Remarks:
1. Integrator windup
b
y
a
r*
u
a
b
umax
τ
6.2 Indirect design method
2. Modification of D control
k
6.2 Indirect design method
e
D control
1
Modification of D control
D control
Modification of D control
6.2 Indirect design method
Stepresponse method
a=RL
6.2 Indirect design method
Exercise:
1. , T=1, using step invariance, backward rectangle rule, bilinear transformation, prewarping bilinear transformation method to discretize D(s).
Where have prewarping bilinear at , at , .
2. PID controller
a. Using backward rectangle rule to discretize D(s). T=0.1.
b. Suppose the input signal is e(t) and output signal is u(t), determine
the difference expression of the u(k) when realizing on computer.
c. Determine the analytical solution of u(k) when e(k) is unit step.
_
The controller system with time delay
6.2.4 Smith predictor  controllers for system with time delay
(1) The problem of the control of the systems with time delay
(2) Traditional methods
and its characteristic equation is
(3) Smith predictor
Figure 6.6 Block diagram of a Smithpredictor
Smith predictor
6.2 Indirect design method
and its characteristic equation is
1. Design D(s) for Gp firstly.
2. Realize the controller as the figure shown in Fig. 6.6.
Example 6.2
6.2 Indirect design method
6.2 Indirect design method
6.2 Indirect design method
6.2 Indirect design method
_
Typical Digital Control System
6.3.1 Rootlocus method
(1) Root locus in zplane
6.3 Direct design method
6.3 Direct design method
6.3 Direct design method
Difference with that of continuous system:
1. Has a high density poles.
2. Has more zeros than that of continuous system.
3. The critical gain is found by the intersection of root loci and unit disc.
6.3 Direct design method
6.3 Direct design method
(2) Relationship between dynamic specification and poles location in
z domain
6.3 Direct design method
6.3 Direct design method
6.3 Direct design method
2. Estimate the desired , n and r from the continuous time response
specifications.
From the equation
and the given step response overshoot , we can know the value of
the damping ratio , and the corresponding area on the zplane.
From the equation
and the given rise time tr, we can ascertain the area corresponding
to the value n.
6.3 Direct design method
From the equation
(for 5 error band)
(for 5 error band)
and the given settling time, we can compute the radius r=eRe(s)T on the zplane.
3. Mark the region of acceptable closedloop pole locations on the
plane according to , n and r.
6.3 Direct design method
Example 6.3 Zplane Specifications
Indicate on a zplane map the region of acceptable closedloop poles for the
following specifications:
Sampling rate 0.2 sec, Overshoot to a step input less than 16, Settling time
to 2 to be less than 1 sec, Risetime less than 0.55 sec.
Solution:
1. a damping ratio of 0.5039. The standard grid of the zplane shows the
curve corresponding to = 0.504.
2. natural frequency of n 4.4179, With the requirement that the roots
correspond to a natural frequency greater than n=0.884, we need a plot
on the standard grid corresponding to N = 10Tn/ 2.8125.
3. the roots in the zplane must be inside a circle of radius r exp(4T/1)=
0.4493.
The curves corresponding to these criteria are marked in Fig. 6.11.
6.3 Direct design method
Fig. 6.11 Plot of acceptable pole locations in the zplane
(3) Definition and plotting rules of z domain root locus
Angle condition:
Magnitude condition:
6.3 Direct design method
General Procedure for Constructing Root Loci :
1. Obtain the characteristic equation
1+F(z)=0
and then rearrange this equation so that the parameter of interest,
such as gain K, appears as the multiplying factor in the form
From the factored form of the openloop pulse transfer function,
locate the openloop poles and zeros in the z plane.
2. Find the starting points and terminating points of the root loci. Find
also the number of separate branches of the root loci.
6.3 Direct design method
3. Determine the root loci on the real axis.
4. Determine the asymptotes of the root loci.
where n, m= number of finite poles and zeros of F(z).
If the abscissa of the intersection of the asymptotes and the real
axis is denoted by a, then
6.3 Direct design method
5. Find the breakaway and breakin points.
If the characteristic equation 1+F(z)=0
is written as
where KB(z)/A(z)=F(z), then
And the breakaway and breakin points (which correspond to multiple roots) can be determined from the roots of
6.3 Direct design method
6. Determine the angle of departure (or angle of arrival) of the root loci
from the complex poles (or at the complex zeros).
7. Find the points where the root loci cross the imaginary axis.
Set z = jv in the characteristic equation
1+F(jv)=0
Let Re[1+F(jv)]=0 and Im[1+F(jv)]=0
The values of v and K thus found give the location at which the root loci cross the imaginary axis and the value of the corresponding gain K, respectively.
8. Any point on the root loci is a possible closedloop pole.
(1) A particular point will be a closedloop pole when the value of gain K satisfies the magnitude condition.
(2) The magnitude condition enables us to determine the value of gain K at any specific root location on the locus.
9. Find the points where the root loci cross the unit circle.
(1) Find the critical gain K.
(2) The characteristic eigenvalues with critical gain K are the points
where the root loci cross the unit circle.
F(z)=1
6.3 Direct design method
6.3 Direct design method
4. Find the points where the root loci cross the unit circle.
0.905
1
0.954
0.995
2.934
6.3 Direct design method
6.3 Direct design method
Example:
6.3 Direct design method
Example:
6.3 Direct design method
Example:
6.3 Direct design method
Example:
6.3 Direct design method
Example:
Angle of departure
=180(1)
=180(90 75 )
=165
6.3 Direct design method
Example:
6.3 Direct design method
Example: root locus for system
Consider the system shown in Fig. 6.13. Assume that the digital controller is of the integral type, or that
6.3 Direct design method
Let us draw root locus diagrams for the system for three values of the sampling period T: 0.5sec, 1 sec, and 2 sec. Let us also determine the critical value of K for each case. And finally let us locate the closedloop poles corresponding to K=2 for each of the three cases.
We shall first obtain the z transform of Gh(s)Gp(s):
6.3 Direct design method
The feedforward pulse transferfunction becomes
The characteristic equation is
1. Sampling period = 0.5 sec:
G(z) has poles at z = 1 and z = 0.6065 and a zero at z = 0. The
breakaway point and breakin point are determined by writing the
characteristic equation as
6.3 Direct design method
z = 0.7788 and z =  0.7788
Notice that substitution of 0.7788 for z in K yields K = 0.1244, while letting z =  0.7788 yields K = 8.041. Since both K values are positive, z = 0.7788 is the actual breakaway point and z =  0.7788 is the actual breakin point. Fig. 6.14(a) shows the root locus diagram when T = 0.5 sec.
6.3 Direct design method
6.3 Direct design method
The critical value of gain K for this case is obtained as follows:
or K = 8.165
The critical gain Kc is thus 8.165. The closedloop poles corresponding to K = 2 can be found to be
z1 = 0.4098 + j0.6623 and z2 = 0.4098  j0.6623
these closedloop poles are indicated by dots in the root locus diagram.
6.3 Direct design method
2. Sampling period T = 1 sec
G(z) has poles at z = 1 and z = 0.3679 and a zero at z = 0. The breakaway point and breakin point are found to be z = 0.6065 and z = 0.6065, respectively. The corresponding gain values are K = 0.2449 and K = 4.083, respectively. Fig. 6.14(b) shows the root locus diagram when T = 1 sec. The critical value of gain K is 4.328. The closedloop poles corresponding to K = 2 h are found to be z1 = 0.05185 + j0.6043 and z2 = 0.05185  j0.6043 and are shown in the root locus diagram by dots.
6.3 Direct design method
6.3 Direct design method
3. Sampling period T = 2 sec:
Hence, G(z) has poles at z = 1 and z = 0.1353 and a zero at z = 0. The breakaway point and breakin point are found to be z = 0.3678 and z = 0.3678, respectively. The corresponding gain values are
K = 0.4622 and K = 2.164, respectively. Fig. 6.14(c) shows the root locus diagram when T = 2 sec. The critical value of gain K is 2.626. The closedloop poles corresponding to K = 2 are found to be
z1 = 0.2971 + j0.2169 and z2 = 0.2971  j0.2169
and are shown in the root locus diagram by dots.
6.3 Direct design method
6.3 Direct design method
(4) Design digital controllers in z domain
The structure of the controller:
Proportional controller: D(z)=K
Lead compensation:
Lag compensation:
6.3 Direct design method
6.3 Direct design method
The effect which the location of zero and pole have on the root locus.
zero a changes from 1.5, 1, 0.5 to 0.
pole b changes from 0.368, 0.1, to 0.
6.3 Direct design method
6.3 Direct design method
6.3 Direct design method
Example 6.4 Discrete Root Locus Design
Design controller for
with sampling rate T = 0.2 sec. The dynamic response specification is as the example 6.3.
6.3 Direct design method
Solution:
Its root locus is shown in the following figures.
6.3 Direct design method
6.3 Direct design method
6.3 Direct design method
a=0.312+0.379i;
K=(a*a1)/(0.736*a+0.718)
K= 0.4774
6.3 Direct design method
6.3 Direct design method
6.3 Direct design method
G (z)
Y (s)
T
R (s)
G (s)
ZOH
k
_
6.3 Direct design method
Exercise:
1. , draw the root locus, line out the breakaway and breakin points, and point where the root locus cross the unit circle and corresponding critical K value.
2. , draw the root locus, line out the breakaway and breakin points, and point where the root locus cross the unit circle and corresponding critical K value.
6.3.2 Deadbeat control
from which we can get the direct design formula
1. How to determine expecting closedloop transfer function .
2. If G(z) has unstable poles or zeros, we cannot use
corresponding zeros or poles of D(z) to cancel them.
(1) Deadbeat control with intersampling ripple
Y(s)
E(s)
R(s)
ZOH
G(s)
D(z)

6.3 Direct design method
Determine (z)
6.3 Direct design method
Note that for a timedomain polynomial inputs, such as a unitstep
input, a unitramp input and a unitacceleration input, their z
transforms may be written as
where P(z) is a polynomial in z1 not including (1 z1) term. For a
unitstep input P(z) = 1 and q = 1; for a unitramp input, P(z) = Tz1
and q= 2, and for a unitacceleration input, P(z) = 1/2 T2z1(1+ z1)
and q=3.
6.3 Direct design method
According to the requirements of veracity and speediness,
a. When G(z) has no time delay, has no unstable zeros or poles
(except the pole at z=1)
To be simple, set F(z)=1, then
6.3 Direct design method
For example:
When the input signal is unit step
q = 1,
6.3 Direct design method
When the input signal is unit ramp
q = 2,
6.3 Direct design method
When the input signal is unit acceleration
q = 3,
6.3 Direct design method
b. When G(z) has time delay = lT , has no unstable zeros or poles
(except the pole at z=1)
c. When G(z) has unstable zeros or poles (except the pole at z=1)
6.3 Direct design method
Unlike the case a, now the coefficients of the H(z) and F(z) should
be computed, we use the condition that (z) and 1 (z) has the
same order to compute these unknown coefficients.
m + u + y = q + v + x = x + y + 1
we obtain: x = m + u  1, y = q + v  1, so the closedloop (z) can be
written as
6.3 Direct design method
where q + v coefficients can be determined through q + v equations
as follows:
Y(z)
R(z)
ZOH
G(s)
D(s)

6.3 Direct design method
Example:
T=1, design deadbeat controller D(z) in response to unit step and
unit ramp signals.
Solution:
q = 1, u = v = 0, m=1, so (z) = z1h0, h0 = 1, so 1(z) = 1 z1, so
the controller is
6.3 Direct design method
The system output in response to a unitstep input r(t) = 1 is
6.3 Direct design method
System output and controller output with 4 intersample points
6.3 Direct design method
For unit ramp input, q = 2, u = v = 0, so (z) = z1 (h0+h1z1),
6.3 Direct design method
6.3 Direct design method
6.3 Direct design method
Example:
T=1, design deadbeat controller D(z) in response to unit ramp.
Solution:
q = 2, u = v = 0, m=2, so (z) = z2(h0+h1z1) ,
6.3 Direct design method
6.3 Direct design method
Example:
T=0.1, design deadbeat controller D(z) in response to unit step.
Solution:
q = 1, u =1, v = 0, m=1, so (z) = z1(1+1.93z1) h0 ,
(2) Deadbeat control without intersampling ripple
6.3 Direct design method
In order to ensure the system without intersampling ripples, the controller output should be zero or constant at steady state, so from above equation we know that U/R should be a finite polynomial. Which also means that (z) should include all the numerator of the G(z), that is, P(z). By now, (z) is
where w is the number of zeros of G(z) except 0 zero.
Example: T=1, design deadbeat controller without intersampling
ripple D(z) in response to unit step .
Solution:
q = 1, u = v = 0, w=1, m=1
6.3 Direct design method
Compared with controller with intersampling ripple
6.3 Direct design method
(3) Compromising method
For example: controller designed for ramp signal, when input signal
is step, the output has a very large overshoot. See example:
T=1, design deadbeat controller D(z) in response to unit ramp input.
Solution:
6.3 Direct design method
When input is step, the output is:
When input is acceleration, the output is:
6.3 Direct design method
6.3 Direct design method
6.3 Direct design method
Compromising method is as follows:
See the above example:
Choose d = 0.5
6.3 Direct design method
Choose d = 0.7
Exercise:
1. Design deadbeat controller without intersampling ripple D(z) in
response to unit step and give the output signal and error signal.
2. Design deadbeat controller without intersampling ripple D(z) in
response to unit ramp and give the output signal and error signal.
3. T=1, design deadbeat controller without intersampling ripple
D(z) in response to unit ramp and give the output signal and
error signal.
4. T=1 ,Compromise design controller D(z) with parameter d. (The
beginning design is according to deadbeat controller without
intersampling ripple D(z) in response to unit ramp )
6.3.3 Dahlin algorithm
(1) Digital controller
Process is always
Dahlin algorithm is an analytical design method, so we should find
a expecting closedloop system :
where = NT, N is an integer.
6.3 Direct design method
When
When
(2) Ringing
When
There is no ringing.
When
So the RA is
6.3 Direct design method
when
6.3 Direct design method
(3) Eliminating ringing
a. Let z=1 in the ringing terms.
For example:
where =NT, , try to determine the controller which has eliminating ringing terms.
b. Select certain T and Tτ
(4) The procedure to design DDS with Dahlin
a. Determine Tτand the limit of RA.
b. Determine T according to the limit of RA.
c. Determine N, τ=NT.
d. Compute G(z) and Φ(z).
e. Compute D(z).
Indirect design
Discretion
PID
Position/absolute algorithm
incremental algorithm
Smith predictor
Direct design
Root locus
Deadbeat control
with intersampling ripple
without intersampling ripple
compromising method
Dahlin algorithm
1. stable →unstable
Kp: response timely
Ti: larger Ti, weaker integration; larger Ti, longer time to delete static error and smaller overshoot, higher stability
Td: faster response, smaller overshoot and overcome oscillation
Position algorithm:
Incremental algorithm:
1. Design D(s) for Gp firstly.
2. Realize the controller as the figure
Definition and plotting rules of z domain root locus
Angle condition:
Magnitude condition:
Design procedure:
1. Mark the region of acceptable closedloop pole locations on the z plane
according to the specification;
2. Compute G(z);
3. Draw the root locus of openloop transfer function;
4. Design controller;
5. Simulation validation;
6. If the controller does not satisfy the specification, we should return to
step4.
Root Locus based Design
Estimate the desired , nand r from the continuous time response specifications.
or
Root Locus based Design
General Procedure for Constructing Root Loci :
1. locate the openloop poles and zeros in the z plane.
2. Find the starting points, terminating points and the number of separate branches of the root loci.
3. Determine the root loci on the real axis.
4. Determine the asymptotes of the root loci.
Root Locus based Design
5. Find the breakaway and breakin points.
6. Determine the angle of departure (or angle of arrival) of the root
loci from the complex poles (or at the complex zeros).
Angle=180°+∑(angle of zeros) ∑(angle of poles)
7. Find the points where the root loci cross the unit circle.
(1) Find the critical gain K.
(2) The characteristic eigenvalues with critical gain K are the points
where the root loci cross the unit circle.
Root Locus based Design
(1) Deadbeat control with intersampling ripple
a. When G(z) has no time delay, has no unstable zeros or poles
(except the pole at z=1)
To be simple, set F(z)=1, then
b. When G(z) has time delay = lT , has no unstable zeros or
poles (except the pole at z=1)
c. When G(z) has unstable zeros or poles (except the pole at z=1)
(2) Deadbeat control without intersampling ripple
(3) Compromising method
(1) Dahlin algorithm
Dahlin algorithm is an analytical design method, so we should find
a expecting closedloop system :
(2) Ringing
6.3 Direct design method
(3) Eliminating ringing
a. Let z=1 in the ringing terms.
b. Select certain T and Tτ
(4) The procedure to design DDS with Dahlin
a. Determine Tτand the limit of RA.
b. Determine T according to the limit of RA.
c. Determine N, τ=NT.
d. Compute G(z) and Φ(z).
e. Compute D(z).
b. Select certain T and Tτ
(4) The procedure to design DDS with Dahlin
a. Determine Tτand the limit of RA.
b. Determine T according to the limit of RA.
c. Determine N, τ=NT.
d. Compute G(z) and Φ(z).
e. Compute D(z).
Homework
1. , T=1, using step invariance, backward rectangle rule, bilinear transformation, prewarping bilinear transformation method to discretize D(s).
Where have prewarping bilinear at , at , .
Solution:
(1) step invariance
(2) backward rectangle rule
Homework
(3) bilinear transformation
(4) prewarping bilinear transformation
Homework
2. PID controller
a. Using backward rectangle rule to discretize D(s). T=0.1.
b. Suppose the input signal is e(t) and output signal is u(t), determine
the difference expression of the u(k) when realizing on computer.
c. Determine the analytical solution of u(k) when e(k) is unit step.
Solution:
a.
b.
c.
Homework
3. , draw the root locus, line out the breakaway and breakin points, and point where the root locus cross the unit circle and corresponding critical K value.
Solution:
Breakaway point：0.894
Breakin point: 0.6935
Kc＝3.27
Point where the root locus cross the unit circle:（1,0）
G (z)
Y (s)
T
R (s)
G (s)
ZOH
k
_
Homework
4. , draw the root locus, line out the breakaway and breakin points, and point where the root locus cross the unit circle and corresponding critical K value.
Solution:
Breakaway point：0.648
Breakin point: 2.084
Kc＝2.39
Point where the root locus cross the unit circle:（0.244j0.970）
5. Design deadbeat controller without intersampling ripple D(z) in
response to unit step and give the output signal and error signal.
Solution:
6. Design deadbeat controller without intersampling ripple D(z) in
response to unit ramp and give the output signal and error signal.
Solution:
7. T=1, design deadbeat controller without intersampling ripple
D(z) in response to unit ramp and give the output signal and
error signal.
Solution:
8. T=1 ,Compromise design controller D(z) with parameter d. (The
beginning design is according to deadbeat controller without
intersampling ripple D(z) in response to unit ramp )
Solution:
, 0 < d < 1