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# Chapter 6 Classic Design - PowerPoint PPT Presentation

Chapter 6 Classic Design. 6.1 Introduction. Figure 6.1 Typical CCS. Figure 6.2 Simplified CCS framework. There are two kinds of design methods for the design of CCS, i.e., indirect design method and direct design method. 6.2 Indirect design method. Discretize.

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Chapter 6 Classic Design

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Chapter 6

Classic Design

### 6.1 Introduction

Figure 6.1 Typical CCS

Figure 6.2 Simplified CCS framework

There are two kinds of design methods for the design of CCS, i.e., indirect design method and direct design method.

### 6.2 Indirect design method

Discretize

Figure 6.3 Indirect design method

Simple; Abundant experience in continuous design

Have a larger phase delay than that of continuous-time system

### 6.2 Indirect design method

Concrete procedure:

1.Choose sampling period, and design pre-antialiasing filter

2.Design or discretize continuous controller

3.Test the performance of the discrete system

4. If the system cannot meet the specification, there are three ways to improve it.

a. Choose the more appropriate discretized method

b. Increase sampling frequency

c. Modify the original continuous controller

### 6.2 Indirect design method

6.2.1 Approximations based on transfer functions

The system’s transfer function

is equivalent to the differential

equation

(6.1)

where a=1/(RC)

Figure 6.4 Continuous time filter

### 6.2 Indirect design method

1.Numerical integration

• If we write Eq. (6.1) in integral form as following

• Many rules have been developed based on how the incremental area term is approximated.

• Three possibilities are sketched in Fig. 6.5 which is called forward rectangular rule, backward rectangular rule and trapezoid rule respectively.

### 6.2 Indirect design method

Figure 6.5 Sketches of three ways the area under the curve from

kT to kT+T can be approximated

### 6.2 Indirect design method

(1) forward rectangular rule (also known as Euler’s rule)

• We approximate the area by the rectangle looking forward from kT-T and take the amplitude of the rectangle to be the value of the integrand at kT-T. The width of the rectangle is T. The result is an equation in the first approximation, u1

• The transfer function corresponding to the forward rectangular rule in this case is

### 6.2 Indirect design method

• Remarks

• 1. Very simple even for large system

• 2. Stable perhaps will obtain unstable, so the former rectangular

• rule can’t be used in the real application

• 3. Steady-state gain is invariant, i.e., H(s)|s=0=H(z)|z=1

### 6.2 Indirect design method

(2) backward rectangular rule

• we approximate the area by the rectangle looking backward from kT toward kT-T. The equation for u2 is

• The corresponding transfer function is

### 6.2 Indirect design method

• Remarks

• 1. Stable will obtain stable

• 2. There are large distortions on dynamic response and frequency

• response properties.

• 3. T should be smaller.

• 4. Steady-state gain is invariant, i.e., H(s)|s=0=H(z)|z=1

### 6.2 Indirect design method

(3) trapezoid rule

• Taking the area to be that of the trapezoid formed by the average of the previously selected rectangles. The approximating difference equation is

• The corresponding transfer function from the trapezoid rule is

### 6.2 Indirect design method

• Remarks

• 1. Stable will obtain stable and is not same as z transform.

• 2. Have frequency distortion or warping

• 3. Frequency pre-warping can decrease the distortion on frequency

• response.

• 4. Steady-state gain is invariant, i.e., H(s)|s=0=H(z)|z=1

### 6.2 Indirect design method

(4) Frequency pre-warping

set

Then

If is small ; ,

Example 6.1

### 6.2 Indirect design method

2.Input response invariance--Step invariance

• If the input signal is constant over the sampling intervals, equation

H(z) = (1 – z-1) Z{G(s)/s}

gives an appropriate pulse-transfer function H(z) for a given transfer function G(s).

### 6.2 Indirect design method

Remarks:

1. Stable obtain stable

2. Frequency folding phenomena, but thanks to the low-pass

characteristics of the ZOH, it is a little better.

3. Complex computation for large-scale systems

4. Steady-state value is invariant, i.e., G(s)|s=0=H(z)|z=1

6.2 Indirect design method

Example:

bode(1,[1 1])

hold on

dbode([1 1],[3 -1],1)

6.2 Indirect design method

Example:

sysc=tf([1 1 9],[1 2 9]);

sysdt=c2d(sysc,1,'tustin')

Transfer function:

0.8824 z^2 + 0.5882 z + 0.6471

------------------------------

z^2 + 0.5882 z + 0.5294

Sampling time: 1

>> bode(sysc)

>> hold on

>> dbode([0.8824 .5882 .6471],[1 .5882 .5294],1)

6.2 Indirect design method

Example:

sysc=tf([1 1 9],[1 2 9]);

sysdp=c2d(sysc,1,'prewarp',3)

Transfer function:

0.9775 z^2 + 1.891 z + 0.9326

-----------------------------

z^2 + 1.891 z + 0.9101

Sampling time: 1

>> dbode([.9775 1.891 .9326],[1 1.891 .9101],1)

>> bode(sysc)

>> hold on

>> dbode([0.8824 .5882 .6471],[1 .5882 .5294],1)

6.2 Indirect design method

Comparison of discretization methods

### 6.2 Indirect design method

6.2.2 Approximations based on state models

(1) Forward rectangular rule is to replace s with (z-1)/T

is a state-space formula for the forward rule equivalent.

### 6.2 Indirect design method

(2) For the backward rule, substitute with the result

which corresponds to the time domain equation

### 6.2 Indirect design method

(3) Finally, for the trapezoid or bilinear rule, the z-transform equivalent is obtained

### 6.2 Indirect design method

• These results can be tabulated for convenient reference. Suppose we have a continuous system described by

• Then a discrete equivalent at sampling period T will be described by the equations

where , ,  and J are given as follows:

### 6.2 Indirect design method

6.2.3 Digital PID controllers

(1) Analog PID controllers

e

1

t

t0

u

Kp

u0

t0

t

• P control

e

1

t

t0

Kp

u

Kp

u0

Ti

t0

t

• PI control

e

1

t0

t

Kp

u

Kp

u0

Ti

t0

t

• PID control

### 6.2 Indirect design method

(2) Digital PID controllers

• Position algorithm

Suppose t= kT, k= 0,1,2,…

So e(t) = e(kT)

We call it position algorithm or an absolute algorithm.

### 6.2 Indirect design method

The output of the controller is the absolute value of the control signal, for instance, a valve position.

### 6.2 Indirect design method

• Incremental algorithm

we call it incremental algorithm.

or

6.2 Indirect design method

In an incremental algorithm, the output of the controller should

then represent the increments of the control signal.

• Advantages of the incremental algorithm

• When there exists failure in computer, the influence on the

• system is smaller.

• 2. Impact of the control is smaller when changing between manual and automatic mode.

### 6.2 Indirect design method

• Pulse-transfer function for PID controllers

which is equivalent to the following equation

6.2 Indirect design method

P control

PI control

PD control

6.2 Indirect design method

Remarks:

1. Integrator windup

b

y

a

r*

u

a

b

umax

τ

6.2 Indirect design method

2. Modification of D control

k

6.2 Indirect design method

e

D control

1

Modification of D control

D control

Modification of D control

6.2 Indirect design method

• Tuning of PID control parameters

Step-response method

a=RL

6.2 Indirect design method

Exercise:

1. , T=1, using step invariance, backward rectangle rule, bilinear transformation, prewarping bilinear transformation method to discretize D(s).

Where have prewarping bilinear at , at , .

2. PID controller

a. Using backward rectangle rule to discretize D(s). T=0.1.

b. Suppose the input signal is e(t) and output signal is u(t), determine

the difference expression of the u(k) when realizing on computer.

c. Determine the analytical solution of u(k) when e(k) is unit step.

_

The controller system with time delay

### 6.2 Indirect design method

6.2.4 Smith predictor - controllers for system with time delay

(1) The problem of the control of the systems with time delay

• The time delay is aroused by the delay of transition of the materials and energies

• In 1950s, Smith proposed a compensation model for the systems with time delay, which is difficult to be realized with analog controller

### 6.2 Indirect design method

and its characteristic equation is

### 6.2 Indirect design method

(3) Smith predictor

Figure 6.6 Block diagram of a Smith-predictor

Smith predictor

6.2 Indirect design method

and its characteristic equation is

### 6.2 Indirect design method

• The controller consists of a controller D(s) and a loop around it that contains a predictor model. The controller D(s) is designed as if the time delay T in the process was absent and the feedback around the controller ensures that the system with the time delay will be well behaved.

• So procedure for smith predictor is as follows:

1. Design D(s) for Gp firstly.

2. Realize the controller as the figure shown in Fig. 6.6.

### 6.2 Indirect design method

Example 6.2

• A time-delay process is described by the model

• If there were no time-delays, a PI-controller with gain 0.4 and integration time Ti = 0.4 would give good control.

• This PI-controller will not give good control if the process has a time delay. To obtain good PI-regulation, it is necessary to have a gain of 0.1 and Ti = 0.5.

6.2 Indirect design method

6.2 Indirect design method

6.2 Indirect design method

6.2 Indirect design method

### 6.2 Indirect design method

• If there is a step disturbance introduced in the output at t = 20. In the following figure We also show the response of the Smith-predictor.

• Notice that the step response is faster and that the system recovers faster from the load disturbance.

### 6.3 Direct design method

• Advantages of indirect design method

• Simple; Abundant experience in continuous design

• Disadvantages of indirect design method

• Have a larger phase delay than that of continuous-time system

• Dynamic specifications of the system is strongly related to the sampling period

• Advantages of direct design method

• No discretion error

• No need on high sampling frequency

_

Typical Digital Control System

### 6.3 Direct design method

6.3.1 Root-locus method

(1) Root locus in z-plane

• The close-loop transfer function of (b) is

### 6.3 Direct design method

• The characteristic equation of (b) is

• The characteristic equation of (a) is

• So the definition and plotting rules of s domain root locus is applicable to z domain.

### 6.3 Direct design method

• The most common root locus is a plot of the roots of a closed-loop characteristic polynomial in the s-planes as the loop gain is varied from 0 to  when zeros and poles of open-loop transfer function are known.

• Root locus of the discrete system is a plot of the roots of a closed-loop characteristic polynomial in the z-planes as the loop gain is varied from 0 to  when zeros and poles of open-loop transfer function are known.

6.3 Direct design method

6.3 Direct design method

6.3 Direct design method

Difference with that of continuous system:

1. Has a high density poles.

2. Has more zeros than that of continuous system.

3. The critical gain is found by the intersection of root loci and unit disc.

6.3 Direct design method

• Design procedure:

• Mark the region of acceptable closed-loop pole locations on the z

• plane according to the specification;

• 2. Compute G(z);

• 3. Draw the root locus of open-loop transfer function;

• 4. Design controller;

• 5. Simulation validation;

• 6. If the controller does not satisfy the specification, we should return to step4.

6.3 Direct design method

(2) Relationship between dynamic specification and poles location in

z domain

6.3 Direct design method

• Obtain a plot of the z-plane showing lines of fixed damping and n. The MATLAB command zgrid will do this, plotting  in steps of 0.1 from 0.1 to 0.9 and n=N/10T for integer N from 1 to 10. An example is shown in Fig. 6.10.

6.3 Direct design method

6.3 Direct design method

2. Estimate the desired , n and r from the continuous -time response

specifications.

From the equation

and the given step response overshoot , we can know the value of

the damping ratio , and the corresponding area on the z-plane.

From the equation

and the given rise time tr, we can ascertain the area corresponding

to the value n.

6.3 Direct design method

From the equation

(for 5 error band)

(for 5 error band)

and the given settling time, we can compute the radius r=eRe(s)T on the z-plane.

3. Mark the region of acceptable closed-loop pole locations on the

plane according to , n and r.

6.3 Direct design method

Example 6.3 Z-plane Specifications

Indicate on a z-plane map the region of acceptable closed-loop poles for the

following specifications:

Sampling rate 0.2 sec, Overshoot to a step input less than 16, Settling time

to 2 to be less than 1 sec, Rise-time less than 0.55 sec.

Solution:

1. a damping ratio of  0.5039. The standard grid of the z-plane shows the

curve corresponding to  = 0.504.

2. natural frequency of n 4.4179, With the requirement that the roots

correspond to a natural frequency greater than n=0.884, we need a plot

on the standard grid corresponding to N = 10Tn/ 2.8125.

3. the roots in the z-plane must be inside a circle of radius r exp(4T/-1)=

0.4493.

The curves corresponding to these criteria are marked in Fig. 6.11.

6.3 Direct design method

Fig. 6.11 Plot of acceptable pole locations in the z-plane

### 6.3 Direct design method

(3) Definition and plotting rules of z domain root locus

• Root locus of the discrete system is a plot of the roots of a closed-loop characteristic polynomial in the z-planes as the loop gain is varied from 0 to  when zeros and poles of open-loop transfer function are known.

• Define the characteristic equation as

Angle condition:

Magnitude condition:

6.3 Direct design method

General Procedure for Constructing Root Loci :

1. Obtain the characteristic equation

1+F(z)=0

and then rearrange this equation so that the parameter of interest,

such as gain K, appears as the multiplying factor in the form

From the factored form of the open-loop pulse transfer function,

locate the open-loop poles and zeros in the z plane.

2. Find the starting points and terminating points of the root loci. Find

also the number of separate branches of the root loci.

6.3 Direct design method

3. Determine the root loci on the real axis.

4. Determine the asymptotes of the root loci.

where n, m= number of finite poles and zeros of F(z).

If the abscissa of the intersection of the asymptotes and the real

axis is denoted by a, then

6.3 Direct design method

5. Find the breakaway and break-in points.

If the characteristic equation 1+F(z)=0

is written as

where KB(z)/A(z)=F(z), then

And the breakaway and break-in points (which correspond to multiple roots) can be determined from the roots of

6.3 Direct design method

6. Determine the angle of departure (or angle of arrival) of the root loci

from the complex poles (or at the complex zeros).

### 6.3 Direct design method

7. Find the points where the root loci cross the imaginary axis.

Set z = jv in the characteristic equation

1+F(jv)=0

Let Re[1+F(jv)]=0 and Im[1+F(jv)]=0

The values of v and K thus found give the location at which the root loci cross the imaginary axis and the value of the corresponding gain K, respectively.

### 6.3 Direct design method

8. Any point on the root loci is a possible closed-loop pole.

(1) A particular point will be a closed-loop pole when the value of gain K satisfies the magnitude condition.

(2) The magnitude condition enables us to determine the value of gain K at any specific root location on the locus.

9. Find the points where the root loci cross the unit circle.

(1) Find the critical gain K.

(2) The characteristic eigenvalues with critical gain K are the points

where the root loci cross the unit circle.

|F(z)|=1

6.3 Direct design method

• Example:

• Locate the open-loop poles and zeros in the z plane. There are

• two separate branches and symmetrically located aside real axis.

• 2. Determine the root loci on the real axis.

• 3. Find the breakaway and break-in points.

6.3 Direct design method

4. Find the points where the root loci cross the unit circle.

0.905

1

0.954

-0.995

-2.934

6.3 Direct design method

6.3 Direct design method

Example:

6.3 Direct design method

Example:

6.3 Direct design method

Example:

6.3 Direct design method

Example:

6.3 Direct design method

Example:

Angle of departure

=180-(1-)

=180-(90 -75 )

=165

6.3 Direct design method

Example:

6.3 Direct design method

Example: root locus for system

Consider the system shown in Fig. 6.13. Assume that the digital controller is of the integral type, or that

6.3 Direct design method

Let us draw root locus diagrams for the system for three values of the sampling period T: 0.5sec, 1 sec, and 2 sec. Let us also determine the critical value of K for each case. And finally let us locate the closed-loop poles corresponding to K=2 for each of the three cases.

We shall first obtain the z transform of Gh(s)Gp(s):

6.3 Direct design method

The feedforward pulse transfer-function becomes

The characteristic equation is

1. Sampling period = 0.5 sec:

G(z) has poles at z = 1 and z = 0.6065 and a zero at z = 0. The

breakaway point and break-in point are determined by writing the

characteristic equation as

6.3 Direct design method

z = 0.7788 and z = - 0.7788

Notice that substitution of 0.7788 for z in K yields K = 0.1244, while letting z = - 0.7788 yields K = 8.041. Since both K values are positive, z = 0.7788 is the actual breakaway point and z = - 0.7788 is the actual break-in point. Fig. 6.14(a) shows the root locus diagram when T = 0.5 sec.

6.3 Direct design method

6.3 Direct design method

The critical value of gain K for this case is obtained as follows:

or K = 8.165

The critical gain Kc is thus 8.165. The closed-loop poles corresponding to K = 2 can be found to be

z1 = 0.4098 + j0.6623 and z2 = 0.4098 - j0.6623

these closed-loop poles are indicated by dots in the root locus diagram.

6.3 Direct design method

2. Sampling period T = 1 sec

G(z) has poles at z = 1 and z = 0.3679 and a zero at z = 0. The breakaway point and break-in point are found to be z = 0.6065 and z = -0.6065, respectively. The corresponding gain values are K = 0.2449 and K = 4.083, respectively. Fig. 6.14(b) shows the root locus diagram when T = 1 sec. The critical value of gain K is 4.328. The closed-loop poles corresponding to K = 2 h are found to be z1 = 0.05185 + j0.6043 and z2 = 0.05185 - j0.6043 and are shown in the root locus diagram by dots.

6.3 Direct design method

6.3 Direct design method

3. Sampling period T = 2 sec:

Hence, G(z) has poles at z = 1 and z = 0.1353 and a zero at z = 0. The breakaway point and break-in point are found to be z = 0.3678 and z = -0.3678, respectively. The corresponding gain values are

K = 0.4622 and K = 2.164, respectively. Fig. 6.14(c) shows the root locus diagram when T = 2 sec. The critical value of gain K is 2.626. The closed-loop poles corresponding to K = 2 are found to be

z1 = -0.2971 + j0.2169 and z2 = -0.2971 - j0.2169

and are shown in the root locus diagram by dots.

6.3 Direct design method

6.3 Direct design method

(4) Design digital controllers in z domain

The structure of the controller:

Proportional controller: D(z)=K

Lag compensation:

6.3 Direct design method

• If the root locus of open-loop transfer function pass the region

• marked by specification, we can choose one point as poles of the closed-loop system, then compute proportional coefficient, i.e. it is a pure proportional controller.

• b. Or else adding a lead compensation, make root locus moving towards left. The bigger zc than pc, the effect is more distinctive. And then choose one point as poles of the closed-loop system, then compute proportional coefficient.

• c. If there is steady-state specification, two above cases all should compute this specification, if the error is big, should add lag compensation to the controller.

6.3 Direct design method

The effect which the location of zero and pole have on the root locus.

zero a changes from -1.5, -1, -0.5 to 0.

pole b changes from 0.368, 0.1, to 0.

6.3 Direct design method

6.3 Direct design method

6.3 Direct design method

Example 6.4 Discrete Root Locus Design

Design controller for

with sampling rate T = 0.2 sec. The dynamic response specification is as the example 6.3.

6.3 Direct design method

Solution:

Its root locus is shown in the following figures.

6.3 Direct design method

6.3 Direct design method

6.3 Direct design method

a=0.312+0.379i;

K=(|a|*|a-1|)/(0.736*|a+0.718|)

K= 0.4774

6.3 Direct design method

6.3 Direct design method

6.3 Direct design method

G (z)

Y (s)

T

R (s)

G (s)

ZOH

k

_

6.3 Direct design method

Exercise:

1. , draw the root locus, line out the breakaway and break-in points, and point where the root locus cross the unit circle and corresponding critical K value.

2. , draw the root locus, line out the breakaway and break-in points, and point where the root locus cross the unit circle and corresponding critical K value.

### 6.3 Direct design method

• It is a analytical design method.

• Assume the expecting closed-loop transfer function is . And  is given by the formula

from which we can get the direct design formula

• Difficulties:

1. How to determine expecting closed-loop transfer function .

2. If G(z) has unstable poles or zeros, we cannot use

corresponding zeros or poles of D(z) to cancel them.

### 6.3 Direct design method

• Definition of the dead-beat control:

• It is an analytical design method for digital controllers that will force the error sequence, when subjected to a specific type of time-domain input, to become zero after a finite number of sampling periods and, in fact, to become zero and stay zero after the minimum possible number of sampling periods.

(1) Dead-beat control with inter-sampling ripple

• Requirements: Veracity; Speediness; Causality; Stability.

Y(s)

E(s)

R(s)

ZOH

G(s)

D(z)

-

6.3 Direct design method

Determine (z)

6.3 Direct design method

Note that for a time-domain polynomial inputs, such as a unit-step

input, a unit-ramp input and a unit-acceleration input, their z

transforms may be written as

where P(z) is a polynomial in z-1 not including (1- z-1) term. For a

unit-step input P(z) = 1 and q = 1; for a unit-ramp input, P(z) = Tz-1

and q= 2, and for a unit-acceleration input, P(z) = 1/2 T2z-1(1+ z-1)

and q=3.

6.3 Direct design method

According to the requirements of veracity and speediness,

a. When G(z) has no time delay, has no unstable zeros or poles

(except the pole at z=1)

To be simple, set F(z)=1, then

6.3 Direct design method

For example:

When the input signal is unit step

q = 1,

6.3 Direct design method

When the input signal is unit ramp

q = 2,

6.3 Direct design method

When the input signal is unit acceleration

q = 3,

6.3 Direct design method

b. When G(z) has time delay = lT , has no unstable zeros or poles

(except the pole at z=1)

### 6.3 Direct design method

c. When G(z) has unstable zeros or poles (except the pole at z=1)

6.3 Direct design method

Unlike the case a, now the coefficients of the H(z) and F(z) should

be computed, we use the condition that (z) and 1- (z) has the

same order to compute these unknown coefficients.

m + u + y = q + v + x = x + y + 1

we obtain: x = m + u - 1, y = q + v - 1, so the closed-loop (z) can be

written as

6.3 Direct design method

where q + v coefficients can be determined through q + v equations

as follows:

Y(z)

R(z)

ZOH

G(s)

D(s)

-

6.3 Direct design method

Example:

T=1, design dead-beat controller D(z) in response to unit step and

unit ramp signals.

Solution:

q = 1, u = v = 0, m=1, so (z) = z-1h0, h0 = 1, so 1-(z) = 1- z-1, so

the controller is

6.3 Direct design method

The system output in response to a unit-step input r(t) = 1 is

6.3 Direct design method

System output and controller output with 4 intersample points

6.3 Direct design method

For unit ramp input, q = 2, u = v = 0, so (z) = z-1 (h0+h1z-1),

6.3 Direct design method

6.3 Direct design method

6.3 Direct design method

Example:

T=1, design dead-beat controller D(z) in response to unit ramp.

Solution:

q = 2, u = v = 0, m=2, so (z) = z-2(h0+h1z-1) ,

6.3 Direct design method

6.3 Direct design method

Example:

T=0.1, design dead-beat controller D(z) in response to unit step.

Solution:

q = 1, u =1, v = 0, m=1, so (z) = z-1(1+1.93z-1) h0 ,

### 6.3 Direct design method

(2) Dead-beat control without inter-sampling ripple

• The inter-sampling ripples are caused by controller, so we should make control signal zero or constant after steady-state is arrived.

6.3 Direct design method

In order to ensure the system without intersampling ripples, the controller output should be zero or constant at steady state, so from above equation we know that U/R should be a finite polynomial. Which also means that (z) should include all the numerator of the G(z), that is, P(z). By now, (z) is

where w is the number of zeros of G(z) except 0 zero.

### 6.3 Direct design method

Example: T=1, design dead-beat controller without inter-sampling

ripple D(z) in response to unit step .

Solution:

q = 1, u = v = 0, w=1, m=1

6.3 Direct design method

Compared with controller with inter-sampling ripple

6.3 Direct design method

### 6.3 Direct design method

(3) Compromising method

• Limitation of the above dead-beat control:

• Closed-loop poles at the origin is very sensitive to system parameter variations. So G(z) should has a high precision.

• A digital control system has excellent transient response characteristics for the input it is designed for, it may exhibit inferior or sometimes unacceptable transient response characteristics for other types of input.

• Compromising method is aiming at the 2nd limitation.

### 6.3 Direct design method

For example: controller designed for ramp signal, when input signal

is step, the output has a very large overshoot. See example:

T=1, design dead-beat controller D(z) in response to unit ramp input.

Solution:

6.3 Direct design method

When input is step, the output is:

When input is acceleration, the output is:

6.3 Direct design method

6.3 Direct design method

6.3 Direct design method

Compromising method is as follows:

See the above example:

Choose d = 0.5

6.3 Direct design method

Choose d = 0.7

### 6.3 Direct design method

Exercise:

1. Design dead-beat controller without inter-sampling ripple D(z) in

response to unit step and give the output signal and error signal.

2. Design dead-beat controller without inter-sampling ripple D(z) in

response to unit ramp and give the output signal and error signal.

### 6.3 Direct design method

3. T=1, design dead-beat controller without inter-sampling ripple

D(z) in response to unit ramp and give the output signal and

error signal.

4. T=1 ,Compromise design controller D(z) with parameter d. (The

beginning design is according to dead-beat controller without

inter-sampling ripple D(z) in response to unit ramp )

### 6.3 Direct design method

6.3.3 Dahlin algorithm

(1) Digital controller

Process is always

Dahlin algorithm is an analytical design method, so we should find

a expecting closed-loop system :

where  = NT, N is an integer.

6.3 Direct design method

When

When

### 6.3 Direct design method

(2) Ringing

• Ringing: The output of digital control has a high-frequency attenuation oscillation with frequency s/2, which is also called ringing.

### 6.3 Direct design method

When

There is no ringing.

When

### 6.3 Direct design method

• RA (ringing amplitude): amplitude of the 1st term of the output of the controller minus that of the 2nd term when stimulated by a unit step input.

So the RA is

6.3 Direct design method

when

6.3 Direct design method

(3) Eliminating ringing

a. Let z=1 in the ringing terms.

For example:

where =NT, , try to determine the controller which has eliminating ringing terms.

### 6.3 Direct design method

b. Select certain T and Tτ

(4) The procedure to design DDS with Dahlin

a. Determine Tτand the limit of RA.

b. Determine T according to the limit of RA.

c. Determine N, τ=NT.

d. Compute G(z) and Φ(z).

e. Compute D(z).

Indirect design

Discretion

PID

-Position/absolute algorithm

-incremental algorithm

Smith predictor

Direct design

Root locus

-with inter-sampling ripple

-without inter-sampling ripple

-compromising method

Dahlin algorithm

### Discretion

1. stable →unstable

• stable →stable

• large distortions on dynamic response and frequency response properties.

• T should be smaller

• stable →stable

• frequency distortion or warping

• 3. decrease the distortion on frequency: frequency pre-warping

### Digital PID Controller

Kp: response timely

Ti: larger Ti, weaker integration; larger Ti, longer time to delete static error and smaller overshoot, higher stability

Td: faster response, smaller overshoot and overcome oscillation

Position algorithm:

Incremental algorithm:

### Smith Predictor

1. Design D(s) for Gp firstly.

2. Realize the controller as the figure

### Root Locus based Design

Definition and plotting rules of z domain root locus

• Root locus of the discrete system is a plot of the roots of a closed-loop characteristic polynomial in the z-planes as the loop gain is varied from 0 to  when zeros and poles of open-loop transfer function are known.

• Define the characteristic equation as

Angle condition:

Magnitude condition:

### Root Locus based Design

Design procedure:

1. Mark the region of acceptable closed-loop pole locations on the z plane

according to the specification;

2. Compute G(z);

3. Draw the root locus of open-loop transfer function;

4. Design controller;

5. Simulation validation;

6. If the controller does not satisfy the specification, we should return to

step4.

Root Locus based Design

Estimate the desired , nand r from the continuous -time response specifications.

or

Root Locus based Design

General Procedure for Constructing Root Loci :

1. locate the open-loop poles and zeros in the z plane.

2. Find the starting points, terminating points and the number of separate branches of the root loci.

3. Determine the root loci on the real axis.

4. Determine the asymptotes of the root loci.

Root Locus based Design

5. Find the breakaway and break-in points.

6. Determine the angle of departure (or angle of arrival) of the root

loci from the complex poles (or at the complex zeros).

Angle=180°+∑(angle of zeros)- ∑(angle of poles)

7. Find the points where the root loci cross the unit circle.

(1) Find the critical gain K.

(2) The characteristic eigenvalues with critical gain K are the points

where the root loci cross the unit circle.

Root Locus based Design

• Design digital controllers in z domain

• The structure of the controller:

• Proportional controller: D(z)=K

• Lag compensation:

(1) Dead-beat control with inter-sampling ripple

• Requirements: Veracity; Speediness; Causality; Stability.

a. When G(z) has no time delay, has no unstable zeros or poles

(except the pole at z=1)

To be simple, set F(z)=1, then

b. When G(z) has time delay = lT , has no unstable zeros or

poles (except the pole at z=1)

c. When G(z) has unstable zeros or poles (except the pole at z=1)

(2) Dead-beat control without inter-sampling ripple

(3) Compromising method

### Dahlin Algorithm

(1) Dahlin algorithm

Dahlin algorithm is an analytical design method, so we should find

a expecting closed-loop system :

### 6.3 Direct design method

(2) Ringing

• Ringing: The output of digital control has a high-frequency attenuation oscillation with frequency s/2, which is also called ringing.

• RA (ringing amplitude): amplitude of the 1st term of the output of the controller minus that of the 2nd term when stimulated by a unit step input.

6.3 Direct design method

(3) Eliminating ringing

a. Let z=1 in the ringing terms.

b. Select certain T and Tτ

(4) The procedure to design DDS with Dahlin

a. Determine Tτand the limit of RA.

b. Determine T according to the limit of RA.

c. Determine N, τ=NT.

d. Compute G(z) and Φ(z).

e. Compute D(z).

### 6.3 Direct design method

b. Select certain T and Tτ

(4) The procedure to design DDS with Dahlin

a. Determine Tτand the limit of RA.

b. Determine T according to the limit of RA.

c. Determine N, τ=NT.

d. Compute G(z) and Φ(z).

e. Compute D(z).

Homework

1. , T=1, using step invariance, backward rectangle rule, bilinear transformation, prewarping bilinear transformation method to discretize D(s).

Where have prewarping bilinear at , at , .

Solution:

(1) step invariance

(2) backward rectangle rule

Homework

(3) bilinear transformation

(4) prewarping bilinear transformation

Homework

2. PID controller

a. Using backward rectangle rule to discretize D(s). T=0.1.

b. Suppose the input signal is e(t) and output signal is u(t), determine

the difference expression of the u(k) when realizing on computer.

c. Determine the analytical solution of u(k) when e(k) is unit step.

Solution:

a.

b.

### Homework

c.

Homework

3. , draw the root locus, line out the breakaway and break-in points, and point where the root locus cross the unit circle and corresponding critical K value.

Solution:

Breakaway point：0.894

Breakin point: -0.6935

Kc＝3.27

Point where the root locus cross the unit circle:（-1,0）

G (z)

Y (s)

T

R (s)

G (s)

ZOH

k

_

Homework

4. , draw the root locus, line out the breakaway and break-in points, and point where the root locus cross the unit circle and corresponding critical K value.

Solution:

Breakaway point：0.648

Breakin point: -2.084

Kc＝2.39

Point where the root locus cross the unit circle:（0.244j0.970）

### Homework

5. Design dead-beat controller without inter-sampling ripple D(z) in

response to unit step and give the output signal and error signal.

Solution:

### Homework

6. Design dead-beat controller without inter-sampling ripple D(z) in

response to unit ramp and give the output signal and error signal.

Solution:

### Homework

7. T=1, design dead-beat controller without inter-sampling ripple

D(z) in response to unit ramp and give the output signal and

error signal.

Solution:

### Homework

8. T=1 ,Compromise design controller D(z) with parameter d. (The

beginning design is according to dead-beat controller without

inter-sampling ripple D(z) in response to unit ramp )

Solution:

, 0 < d < 1