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Calice MAPS Adapter Card Review. M. Noy 26 th June 2007. Overview I. Adapter Card: Connector interface 3x 0.05” pitch IDC header 80 way each 65 Upstream pairs (away from PC) 49 downstream pairs (towards PC) 6 pairs spare LVCMOS to LVDS drivers used to reduce pin count 4V

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Calice maps adapter card review

Calice MAPS Adapter Card Review

M. Noy

26th June 2007

M. Noy. Imperial College London


Overview i
Overview I

  • Adapter Card:

    • Connector interface

      • 3x 0.05” pitch IDC header

      • 80 way each

      • 65 Upstream pairs (away from PC)

      • 49 downstream pairs (towards PC)

      • 6 pairs spare

    • LVCMOS to LVDS drivers used to reduce pin count

    • 4V

      • linear regulator from 5V

M. Noy. Imperial College London





Overview ii
Overview II

  • Board synchronisation interface

    • Allows boards to function as master or slave

    • 4 output clocks

    • 1 input clock

    • 4x data interface

      • 2 send and 2 receive each

    • System will support max. of 4 slaves

  • Laser interface

    • 8x TTL send

    • 8x TTL receive

M. Noy. Imperial College London




Overview iii
Overview III

  • Trigger interface

    • Supposed to replace NIM crate + associated

    • 2x PMT interfaces using

      • fast op-amp

      • Comparator

      • DAC

  • Prototype doesn’t work

    • Sarah did the layout anyway whilst I was on holiday

  • If there’s space (and it works) move to 3 to increase flexibility

M. Noy. Imperial College London



Layout
Layout

M. Noy. Imperial College London


Status to do
Status & To do

  • Currently

    • Quotation requested yesterday

    • Part procurement about 60% done

  • To Do

    • Check interface to Vladimir’s board

    • Make trigger work

      • + Add channel

    • Silk screen

M. Noy. Imperial College London


To do
To do

M. Noy. Imperial College London


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