1 / 42

Lecture 5 Combinational Logic Implementation Using Multiplexers, ROMS, FPGAs

Lecture 5 Combinational Logic Implementation Using Multiplexers, ROMS, FPGAs. Prith Banerjee ECE C03 Advanced Digital Logic Design Spring 1998. Outline. Combinational Logic Implementations Multiplexers Decoders ROMS Field Programmable Logic Arrays

tara-rollins
Download Presentation

Lecture 5 Combinational Logic Implementation Using Multiplexers, ROMS, FPGAs

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Lecture 5Combinational Logic Implementation Using Multiplexers, ROMS, FPGAs Prith Banerjee ECE C03 Advanced Digital Logic Design Spring 1998 ECE C03 Lecture 5

  2. Outline • Combinational Logic Implementations • Multiplexers • Decoders • ROMS • Field Programmable Logic Arrays • READING: Katz 4.2.2, 4.2.3, 4.2.4, 4.2.5, 10.3, Dewey 5.7 ECE C03 Lecture 5

  3. Use of Multiplexers/Selectors Multi-point connections A0 A1 B0 B1 Multiple input sources Sa MUX MUX Sb B A Sum Multiple output destinations Ss DEMUX S0 S1 ECE C03 Lecture 5

  4. General Concept of Using Multiplexers A Z I I A Z 1 0 0 I 0 0 0 0 0 1 I 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 n 2 data inputs, n control inputs, 1 output used to connect 2 points to a single point control signal pattern form binary index of input connected to output n Z = A' I + A I 0 1 Functional form Logical form Two alternative forms for a 2:1 Mux Truth Table ECE C03 Lecture 5

  5. Use of Multiplexers/Selectors I 0 2:1 mux I 1 I 0 I 1 4:1 I mux 2 I 3 I 0 I 1 I 2 I 3 8:1 I mux 4 I 5 I 6 I 7 Z = A' I + A I Z 0 1 A Z = A' B' I0 + A' B I1 + A B' I2 + A B I3 Z A B Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 + A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7 Z n 2 -1 In general, Z = S m I k=0 k k n in minterm shorthand form for a 2 :1 Mux A B C ECE C03 Lecture 5

  6. Alternative Implementation A B I0 Z I1 I2 I3 Transmission Gate Implementation of 4:1 Mux Gate Level Implementation of 4:1 Mux twenty transistors thirty six transistors ECE C03 Lecture 5

  7. Design of Large Multiplexers I 0 8:1 0 4:1 I 1 mux 1 mux I 2 2 3 I S S 2:1 3 1 0 mux I 0 4 4:1 I 1 mux 5 I 2 6 I 3 S S 7 1 0 Large multiplexers can be implemented by cascaded smaller ones Control signals B and C simultaneously choose one of I0-I3 and I4-I7 Control signal A chooses which of the upper or lower MUX's output to gate to Z 0 Z 1 S I 0 0 I 1 S 1 C I 0 2 B C A 0 I 1 3 S 1 Alternative 8:1 Mux Implementation Z C 2 I 0 4 3 S0 S1 I 1 5 S A B C I 0 6 I 1 7 S ECE C03 Lecture 5 C

  8. Multiplexers/Selectors as General Purpose Blocks n-1 2 :1 multiplexer can implement any function of n variables n-1 control variables; remaining variable is a data input to the mux Example: F(A,B,C) = m0 + m2 + m6 + m7 = A' B' C' + A' B C' + A B C' + A B C = A' B' (C') + A' B (C') + A B' (0) + A B (1) A B C F 1 0 C 0 0 0 1 0 0 1 C F 1 0 0 1 0 2 C 1 4:1 F 8:1 0 3 2 MUX 0 1 0 1 0 C MUX 0 4 1 3 0 1 1 0 0 5 S1 S0 1 0 0 0 1 6 0 A B 1 0 1 0 1 7 S2 S1 S0 1 1 0 1 1 A B C 1 1 1 1 "Lookup Table" ECE C03 Lecture 5

  9. Generalization of Multiplexer/Selector Logic I I I 1 2 n 0 0 1 1 0 1 0 1 0 I I 1 n n 1 0 D 1 0 2 8:1 1 3 mux D 4 D 5 D 6 D 7 S S S 2 1 0 … F 0 Four possible configurations of the truth table rows … n-1 Mux control variables 1 single Mux data variable Can be expressed as a function of In, 0, 1 Example: G(A,B,C,D) can be implemented by an 8:1 MUX: K-map Choose A,B,C as control variables G Multiplexer Implementation TTL package efficient May be gate inefficient A B C ECE C03 Lecture 5

  10. Decoders/Demultiplexers n Decoder: single data input, n control inputs, 2 outputs control inputs (called select S) represent Binary index of output to which the input is connected data input usually called "enable" (G) 1:2 Decoder: 3:8 Decoder: O0 = G • S0 • S1 • S2 O1 = G • S0 • S1 • S2 O2 = G • S0 • S1 • S2 O3 = G • S0 • S1 • S2 O4 = G • S0 • S1 • S2 O5 = G • S0 • S1 • S2 O6 = G • S0 • S1 • S2 O7 = G • S0 • S1 • S2 O0 = G • S; O1 = G • S 2:4 Decoder: O0 = G • S0 • S1 O1 = G • S0 • S1 O2 = G • S0 • S1 O3 = G • S0 • S1 ECE C03 Lecture 5

  11. Alternative Implementations /G G Output0 Output0 Select Select Output1 Output1 1:2 Decoder, Active Low Enable 1:2 Decoder, Active High Enable /G G Output0 Output0 Output1 Output1 Output2 Output2 Output3 Output3 Select0 Select1 Select0 Select1 2:4 Decoder, Active Low Enable 2:4 Decoder, Active High Enable ECE C03 Lecture 5

  12. Switch Level Implementations Select Select G Output 0 Select G Output 0 Select Select "0" Select Select Output Select 1 Select Output 1 Select Naive, Incorrect Implementation All outputs not driven at all times Select "0" Select Correct 1:2 Decoder Implementation ECE C03 Lecture 5

  13. Switch Implementation of 2:4 Decoder Select Select 1 0 G Output 0 "0" "0" G Output 1 "0" "0" G Output 2 "0" "0" G Output 3 "0" "0" Operation of 2:4 Decoder S0 = 0, S1 = 0 one straight thru path three diagonal paths ECE C03 Lecture 5

  14. Decoder as a Logic Building Block 0 ABC 1 ABC 2 ABC 3 ABC 3:8 dec 4 ABC 5 ABC 6 ABC 7 S S S ABC 2 1 0 Decoder Generates Appropriate Minterm based on Control Signals Enb A B C Example Function: F1 = A' B C' D + A' B' C D + A B C D F2 = A B C' D' + A B C F3 = (A' + B' + C' + D') ECE C03 Lecture 5

  15. Decoder as a Logic Building Block 0 A B C D 1 A B C D F 1 2 A B C D 3 A B C D 4 A B C D 5 A B C D 6 A B C D 4:16 7 A B C D dec 8 A B C D F 2 9 A B C D 10 A B C D 1 1 A B C D 12 A B C D 13 A B C D 14 A B C D F 3 15 S S S S A B C D 3 2 1 0 Enb A B C D If active low enable, then use NAND gates! ECE C03 Lecture 5

  16. Alternative Implementation of 32:1 Mux 6 EN 1 7 7 1G 1Y3 EN 14 5 6 151 139 7 1Y2 15 151 I31 7 4 3 5 6 A 1B 1 1Y1 3 EN 6 6 2 4 7 1 5 1A 1Y0 14 14 2 EN I5 2 B 5 5 1 Y 5 151 4 7 15 9 3 4 2Y3 15 15 5 151 I23 I4 4 4 1 7 Y 1 2G 6 3 W 2Y2 10 4 5 6 1 1 0 6 6 I3 3 3 EN 2 1 7 6 W 2 5 13 2Y1 11 EN 2 2 2B 14 14 I5 I2 2 2 5 5 9 1 3 5 151 1 C 4 7 Y 14 2Y0 12 4 15 15 3 3 151 I4 I1 1 1 5 I15 4 4 Y 4 2A 7 10 1 1 B 3 0 6 5 6 4 4 1 1 W I3 3 3 I0 0 0 EN 6 6 11 2 6 A 7 W 1 1 5 2 GA EN 9 3 C 2 2 14 14 153 I5 5 5 I2 2 2 S2 3 9 9 1 Y 5 C 1 C 7 4 1 3 3 4 B 3 15 15 151 A3 I4 I1 1 1 5 I7 7 4 4 Y 10 10 1 4 0 B 3 1 S1 6 5 W 6 A 4 1 1 4 4 D A2 I0 0 0 0 I6 I3 3 3 6 11 11 2 7 6 A 2 YA W 5 9 5 C A1 2 2 1 I5 I2 2 2 S0 5 S2 3 C 9 9 E 1 C 4 1 6 B 3 3 A0 5 I4 4 I1 1 1 4 10 10 Y 3 0 B 1 S1 4 4 D A I0 0 0 0 I3 3 11 11 6 A 2 W 9 13 B3 C 1 I2 2 S0 9 9 S2 E C C 1 12 B2 B I1 1 9 10 10 YB B 11 1 B1 S1 A D 0 I0 0 11 11 A 10 B0 1 S2 S0 E C 1 GB S1 SO S1 D 5 S0 2 14 E I31 I23 I15 F(A, B, C, D, E) 151 I7 I6 I5 F(A, B, C, D, E) I4 5 Y 1 I3 6 W I2 I1 1 I0 0 C S2 D S1 E S0 A B Multiplexer + Decoder Multiplexer Only ECE C03 Lecture 5

  17. 5:32 Decoder Y7 G1 Y6 1G 1Y3 G2A Y5 1Y2 139 G2B S4 1Y1 Y4 1B S3 138 Y3 1Y0 1A Y2 C 2Y3 2G Y1 B 2Y2 Y0 A 2Y1 2B 2Y0 2A Y7 G1 Y6 G2A Y5 G2B Y4 138 Y3 Y2 C Y1 B Y0 A Y7 G1 Y6 G2A G2B Y5 Y4 138 Y3 C Y2 B Y1 A Y0 Y7 G1 Y6 G2A G2B Y5 Y4 138 Y3 Y2 C Y1 B Y0 A \Y31 \EN \Y30 \Y29 \Y28 \Y27 \Y26 S2 \Y25 S1 S0 \Y24 \Y23 \EN \Y31 \Y22 \Y21 \Y20 \Y19 . 5:32 S2 \Y18 . Decoder S1 \Y17 . S0 \Y16 Subsystem \Y15 \Y0 \Y14 \Y13 S4 S3 S2 S1 S0 \Y12 \Y11 S2 \Y10 S1 \Y9 S0 \Y8 \Y7 \Y6 \Y5 \Y4 \Y3 S2 \Y2 S1 \Y1 S0 \Y0 ECE C03 Lecture 5

  18. Read-Only Memories +5V +5V +5V +5V ROM: Two dimensional array of 1's and 0's Row is called a "word"; index is called an "address" Width of row is called bit-width or wordsize Address is input, selected word is output n 2 -1 i Word Line 0011 Dec Word Line 1010 j 0 Bit Lines 0 n-1 Address ECE C03 Lecture 5 Internal Organization

  19. Implementing Logic with ROMs A B C F F F F W ord Contents 0 1 2 3 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 1 0 0 1 0 0 ROM 0 1 1 0 0 0 1 8 w ords 1 0 0 1 0 1 1 ¥ 1 0 1 1 0 0 0 4 bits 1 1 0 0 0 0 1 1 1 1 0 1 0 0 F F F F 0 1 2 3 F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C' Address by A B C address outputs ECE C03 Lecture 5

  20. ROMs vs PLAs Memory array 2 words by 2 word n n m bits lines m output n address lines lines Not unlike a PLA structure with a fully decoded AND array! Decoder ROM vs. PLA: ROM approach advantageous when (1) design time is short (no need to minimize output functions) (2) most input combinations are needed (e.g., code converters) (3) little sharing of product terms among output functions ROM problem: size doubles for each additional input, can't use don't cares PLA approach advantangeous when (1) design tool like espresso is available (2) there are relatively few unique minterm combinations (3) many minterms are shared among the output functions PAL problem: constrained fan-ins on OR planes ECE C03 Lecture 5

  21. Read-Only Memories 2764 2764 VPP VPP + + PGM PGM A12 A12 A11 A11 A10 O7 A10 O7 A9 A9 O6 O6 A8 A8 O5 O5 A7 O4 A7 O4 A6 A6 O3 O3 A5 A5 O2 O2 A4 O1 A4 O1 A3 O0 A3 O0 A2 A2 A1 A1 A0 A0 CS CS OE OE A13 /OE A12:A0 2764 2764 VPP VPP + + PGM PGM A12 A12 A11 A11 A10 A10 O7 O7 A9 A9 O6 O6 A8 A8 O5 O5 A7 A7 O4 O4 A6 A6 O3 O3 A5 A5 O2 O2 A4 A4 O1 O1 A3 A3 O0 O0 A2 A2 A1 A1 A0 A0 CS CS OE OE 2764 EPROM 8K x 8 2764 VPP VPP PGM PGM A12 A12 A11 A11 A10 A10 O7 O7 A9 A9 U3 U2 O6 O6 A8 A8 O5 O5 A7 A7 O4 O4 A6 A6 O3 O3 A5 A5 O2 O2 D15:D8 D7:D0 A4 A4 O1 O1 A3 A3 O0 O0 A2 A2 A1 A1 A0 A0 CS CS OE OE U1 U0 16K x 16 Subsystem ECE C03 Lecture 5

  22. Combinational Design with FPGAs Programmable Logic Devices = PLD PALs, PLAs = 10 - 100 Gate Equivalents Field Programmable Gate Arrays = FPGAs • Altera MAX Family • Actel Programmable Gate Array • Xilinx Logical Cell Array 100 - 1000(s) of Gate Equivalents! ECE C03 Lecture 5

  23. Altera Erasable Programmable Logic Devices Historical Perspective: PALs – same technology as programmed once bipolar PROM EPLDs — CMOS erasable programmable ROM (EPROM) erased by UV light Altera building block = MACROCELL CLK Clk MUX 8 Product Term AND-OR Array + Programmable MUX's Output pad I/O Pin AND MUX Q ARRAY Invert Control F/B Seq. Logic Block MUX Programmable polarity Programmable feedback ECE C03 Lecture 5

  24. Altera EPLDs Altera EPLDs contain 8 to 48 independently programmed macrocells Personalized by EPROM bits: Global Synchronous Mode CLK Clk MUX 1 Flipflop controlled by global clock signal local signal computes output enable OE/Local CLK Q EPROM Cell Global CLK Clk Asynchronous Mode MUX 1 Flipflop controlled by locally generated clock signal OE/Local CLK Q EPROM Cell + Seq Logic: could be D, T positive or negative edge triggered + product term to implement clear function ECE C03 Lecture 5

  25. Altera EPLDs AND-OR structures are relatively limited Cannot share signals/product terms among macrocells Altera solution: Multiple Array Matrix (MAX) Logic Array Blocks (similar to macrocells) Global Routing: Programmable Interconnect Array LAB A LAB H LAB B LAB G EPM5128: 8 Fixed Inputs 52 I/O Pins 8 LABs 16 Macrocells/LAB 32 Expanders/LAB P I A LAB C LAB F LAB D LAB E ECE C03 Lecture 5

  26. Altera EPLDs LAB Architecture I/O Pad Macrocell I/O ARRAY Block I I/O Pad N P P I U A T Expander S Product Term ARRAY Macrocell P-Terms Expander Terms shared among all macrocells within the LAB Expander P-Terms ECE C03 Lecture 5

  27. Altera EPLDs P22V10 PAL INCREMENT 2904 1 2948 0 4 8 12 16 20 24 28 32 36 40 2992 ASYNCHRONOUS RESET 0 (TO ALL REGISTERS) 3036 FIRST 3080 44 FUSE 3124 88 NUMBERS 3168 132 1 1 3212 OUTPUT 176 3256 LOGIC 220 1 0 18 MACROCEL AR 23 3300 L 264 D Q 0 0 3344 308 3388 0 1 Q 352 5808 3432 SP P - 5818 396 P 3476 R - 5819 3520 R 3564 1 5809 3608 0 6 440 3652 484 3696 528 3740 572 3784 616 OUTPUT 3828 660 LOGIC 22 3872 704 MACROCELL 3916 748 OUTPUT 3960 LOGIC 792 17 MACROCEL 4004 836 L P - 5810 4048 880 R - 5811 4092 4136 2 P - 5820 4180 R - 5821 4224 4268 924 7 968 1012 4312 1056 1100 4356 1144 OUTPUT 4400 1188 LOGIC 21 4444 1232 MACROCELL 4488 1276 4532 OUTPUT 1320 4576 LOGIC 1364 16 MACROCEL P - 5812 4620 1408 L R - 5813 4664 1452 4708 4752 3 P - 5822 4796 R - 5823 4840 1496 8 1540 1584 4884 1628 1672 4928 1716 4972 1760 OUTPUT 5016 1804 LOGIC 20 5060 OUTPUT 1848 MACROCELL 5104 LOGIC 15 1892 MACROCEL 5148 1936 L 5192 1980 P - 5814 5236 2024 R - 5815 5280 2068 P - 5824 5324 R - 5825 2112 4 9 5368 2156 5412 2200 5456 2244 5500 OUTPUT 2288 5544 LOGIC 14 MACROCEL 2332 5588 L 5632 2376 2420 5676 5720 2464 OUTPUT P - 5826 2508 R - 5827 LOGIC 19 2552 MACROCELL 2596 10 2640 2684 SYNCHRONOUS P - 5816 5764 2728 PRESET R - 5817 (TO ALL REGISTERS) 2772 2816 11 13 2860 5 INCREMEN 0 4 8 12 16 20 24 28 32 36 40 T Supports large number of product terms per output Latches and muxes associated with output pins ECE C03 Lecture 5

  28. Actel Programmable Gate Arrays Rows of programmable logic building blocks + rows of interconnect I/O Buffers, Programming and Test Logic I/O Buffers, Programming and Test Logic Anti-fuse Technology: Program Once I/O Buffers, Programming and Test Logic Use Anti-fuses to build up long wiring runs from short segments I/O Buffers, Programming and Test Logic Logic Module Wiring Tracks 8 input, single output combinational logic blocks FFs constructed from discrete cross coupled gates ECE C03 Lecture 5

  29. Actel Logic Module Basic Module is a Modified 4:1 Multiplexer S0 S1 SOA D0 2:1 MUX D1 2:1 MUX Y D2 2:1 MUX D3 R "0" SOB 2:1 MUX Example: Implementation of S-R Latch "0" 2:1 MUX Q "1" 2:1 MUX ECE C03 Lecture 5 S

  30. Actel Interconnect Logic Module Horizontal Track Anti-fuse Vertical Track Interconnection Fabric ECE C03 Lecture 5

  31. Actel Routing Example Logic Module Input Logic Module Logic Module Output Input Jogs cross an anti-fuse minimize the # of jobs for speed critical circuits 2 - 3 hops for most interconnections ECE C03 Lecture 5

  32. Xilinx Logic Cell Arrays CMOS Static RAM Technology: programmable on the fly! All personality elements connected into serial shift register Shift in string of 1's and 0's on power up IOB IOB IOB IOB IOB General Chip Architecture: • Logic Blocks (CLBs) • IO Blocks (IOBs) • Wiring Channels CLB CLB IOB Wiring Channels IOB CLB CLB IOB ECE C03 Lecture 5

  33. Xilinx LCA Architecture Inputs: Tri-state enable bit to output input, output clocks Outputs: input bit Internal FFs for input & output paths Fast/Slow outputs 5 ns vs. 30 ns rise Pull-up used with unused IOBs Program Controlled Options Vcc OUT TS OUTPUT SLEW PASSIVE INV INV SOURCE RATE PULLUP Enable Output PAD MUX Out D Q Output Buffer R Direct In Q D Registered In TTL or CMOS Input Buffer R Clocks Global Reset ECE C03 Lecture 5

  34. Xilinx LCA Architecture Configurable Logic Block: CLB 2 FFs Any function of 5 Variables Global Reset Clock, Clock Enb Independent DIN Reset DIN RD Mux D Q CE Mux X Q1 F A Combinational B Function C Generator D E G Q2 Mux Y RD Mux D Q Clock Mux CE Clock Enable ECE C03 Lecture 5

  35. Xilinx CLB Function Generator Mux Mux Mux Mux Mux Mux Mux Mux CLB Function Generator Q1 A Q1 B Function A F C of 4 F B Variables Function D C of 5 E Variables Q2 D G E Q1 Q2 A Any function of 5 variables B Function G C of 4 Variables D E Q2 Two Independent Functions of 4 variables each ECE C03 Lecture 5

  36. Xilinx CLB Function Generator Mux Mux Mux Mux Mux Q1 A B Function C of 4 Variables E D F Certain Limited Functions of 6 Variables Q2 Q1 G A B Function C of 4 Variables D Q2 ECE C03 Lecture 5

  37. Xilinx Application Examples 5-Input Parity Generator Implemented with 1 CLB: F = A xor B xor C xor D xor E (this is a different parity generator than the one in Chapter 8!) 2-bit Comparator: A B = C D or A B > C D Implemented with 1 CLB: (GT) F = A C + A B D + B C D (EQ) G = A B C D + A B C D + A B C D + A B C D ECE C03 Lecture 5

  38. Xilinx Application Examples n-Input Majority Circuit Assert 1 whenever n/2 or greater inputs are 1 5-input Majority Circuit 9 Input Parity Logic CLB CLB 7-input Majority Circuit CLB CLB CLB CLB n-input Parity Functions 5 input = 1 CLB, 2 Levels of CLBs yield up to 25 inputs! ECE C03 Lecture 5

  39. Xilinx Application Examples 4-bit Binary Adder A3 B3 A2 B2 A1 B1 A0 B0 Cin Full Adder, 4 CLB delays to final carry out CLB CLB CLB CLB Cout S3 S2 S1 C0 S0 C2 C1 A3 B3 A2 B2 A1 B1 A0 B0 Cin 2 x Two-bit Adders (3 CLBs each) yields 2 CLBs to final carry out CLB CLB S2 S0 S3 S1 Cout C2 ECE C03 Lecture 5

  40. Xilinx Interconnect Architecture Direct Connections Interconnect DI CE A DI CE A B B X X C C CLB0 CLB1 K K Y Y Direct Connections Global Long Line Horizontal/Vertical Long Lines Switching Matrix Connections E D R E D R Horizontal Long Line Switching Matrix Horizontal Long Line DI CE A DI CE A B B X X C C CLB3 CLB2 K K Y Y E D R E D R Vertical Global Long Lines Long Line ECE C03 Lecture 5

  41. Comparison of Recent Xilinx Architectures ECE C03 Lecture 5

  42. Summary • Combinational Logic Implementations • Multiplexers • Decoders • ROMS • Field Programmable Logic Arrays • READING: Katz 4.2.2, 4.2.3, 4.2.4, 4.2.5, 10.3, Dewey 5.7 ECE C03 Lecture 5

More Related