Combinational logic
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COMBINATIONAL LOGIC. Overview. Combinational vs. Sequential Logic. At every point in time (except during the switching. transients) each gate output is connected to either. V. or. V. via a low-resistive path. DD. ss. The outputs of the gates assume at all times the value.

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COMBINATIONAL LOGIC

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Combinational logic

COMBINATIONAL LOGIC


Overview

Overview


Combinational vs sequential logic

Combinational vs. Sequential Logic


Static cmos circuit

At every point in time (except during the switching

transients) each gate output is connected to either

V

or

V

via a low-resistive path.

DD

ss

The outputs of the gates assumeat all timesthevalue

of the Boolean function, implemented by the circuit

(ignoring, once again, the transient effects during

switching periods).

This is in contrast to the

dynamic

circuit class, which

relies on temporary storage of signal values on the

capacitance of high impedance circuit nodes.

Static CMOS Circuit


Static cmos

Static CMOS


Nmos transistors in series parallel connection

NMOS Transistors in Series/Parallel Connection

  • Transistors can be thought as a switch controlled by its gate signal

  • NMOS switch closes when switch control input is high


Pmos transistors in series parallel connection

PMOS Transistors in Series/Parallel Connection


Complementary cmos logic style construction cont

Complementary CMOS Logic Style Construction (cont.)


Example gate nand

Example Gate: NAND


Example gate nor

Example Gate: NOR


Example gate complex cmos gate

Example Gate: COMPLEX CMOS GATE


4 input nand gate

4-input NAND Gate

Vdd

Out

GND

In1

In2

In3

In4


Standard cell layout methodology

Standard Cell Layout Methodology


Two versions of a b c

Two Versions of (a+b).c


Logic graph

Logic Graph


Consistent euler path

Consistent Euler Path


Example x ab cd

Example: x = ab+cd


Properties of complementary cmos gates

Properties of Complementary CMOS Gates


Properties of complementary cmos gates1

Properties of Complementary CMOS Gates


Transistor sizing

Transistor Sizing


Propagation delay analysis the switch model

Propagation Delay Analysis - The Switch Model


What is the value of r on

What is the Value of Ron?


Numerical examples of resistances for 1 2 m m cmos

Numerical Examples of Resistances for 1.2mmCMOS


Analysis of propagation delay

Analysis of Propagation Delay


Design for worst case

Design for Worst Case


Influence of fan in and fan out on delay

Influence of Fan-In and Fan-Out on Delay


T p as a function of fan in

tp as a function of Fan-In


Fast complex gate design techniques

Fast Complex Gate - Design Techniques


Fast complex gate design techniques 2

Fast Complex Gate - Design Techniques (2)


Fast complex gate design techniques 3

Fast Complex Gate - Design Techniques (3)


Fast complex gate design techniques 4

Fast Complex Gate - Design Techniques (4)


Example full adder

Example: Full Adder


A revised adder circuit

A Revised Adder Circuit


Ratioed logic

Ratioed Logic


Ratioed logic1

Ratioed Logic


Active loads

Active Loads


Load lines of ratioed gates

Load Lines of Ratioed Gates


Pseudo nmos

Pseudo-NMOS


Pseudo nmos nand gate

Pseudo-NMOS NAND Gate

VDD

GND


Improved loads

Improved Loads


Improved loads 2

Improved Loads (2)


Example

Example


Pass transistor logic

Pass-Transistor Logic


Nmos only switch

NMOS-only switch


Solution 1 transmission gate

Solution 1: Transmission Gate


Resistance of transmission gate

Resistance of Transmission Gate


Pass transistor based multiplexer

S

S

Pass-Transistor Based Multiplexer

S

VDD

GND

In1

In2

S


Transmission gate xor

Transmission Gate XOR


Delay in transmission gate networks

Delay in Transmission Gate Networks


Elmore delay chapter 8

Elmore Delay (Chapter 8)


Delay optimization

Delay Optimization


Transmission gate full adder

Transmission Gate Full Adder


2 nmos only logic level restoring transistor

(2) NMOS Only Logic: Level Restoring Transistor


Level restoring transistor

Level Restoring Transistor


Solution 3 single transistor pass gate with v t 0

Solution 3: Single Transistor Pass Gate with VT=0


Complimentary pass transistor logic

Complimentary Pass Transistor Logic


4 input nand in cpl

4 Input NAND in CPL


Dynamic logic

Dynamic Logic


Example1

Example


Transient response

Transient Response


Dynamic 4 input nand gate

Dynamic 4 Input NAND Gate

VDD

Out

In1

In2

In3

In4

f

GND


Reliability problems charge leakage

Reliability Problems — Charge Leakage


Charge sharing redistribution

Charge Sharing (redistribution)


Charge redistribution solutions

Charge Redistribution - Solutions


Clock feedthrough

Clock Feedthrough


Clock feedthrough and charge sharing

Clock Feedthrough and Charge Sharing


Cascading dynamic gates

Cascading Dynamic Gates


Domino logic

Domino Logic


Domino logic characteristics

Domino Logic - Characteristics


Np cmos

np-CMOS


Np cmos adder

np CMOS Adder


Manchester carry chain adder

Manchester Carry Chain Adder


Cmos circuit styles summary

CMOS Circuit Styles - Summary


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