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COMBINATIONAL LOGIC. Overview. Combinational vs. Sequential Logic. At every point in time (except during the switching. transients) each gate output is connected to either. V. or. V. via a low-resistive path. DD. ss. The outputs of the gates assume at all times the value.

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COMBINATIONAL LOGIC

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COMBINATIONAL LOGIC


Overview


Combinational vs. Sequential Logic


At every point in time (except during the switching

transients) each gate output is connected to either

V

or

V

via a low-resistive path.

DD

ss

The outputs of the gates assumeat all timesthevalue

of the Boolean function, implemented by the circuit

(ignoring, once again, the transient effects during

switching periods).

This is in contrast to the

dynamic

circuit class, which

relies on temporary storage of signal values on the

capacitance of high impedance circuit nodes.

Static CMOS Circuit


Static CMOS


NMOS Transistors in Series/Parallel Connection

  • Transistors can be thought as a switch controlled by its gate signal

  • NMOS switch closes when switch control input is high


PMOS Transistors in Series/Parallel Connection


Complementary CMOS Logic Style Construction (cont.)


Example Gate: NAND


Example Gate: NOR


Example Gate: COMPLEX CMOS GATE


4-input NAND Gate

Vdd

Out

GND

In1

In2

In3

In4


Standard Cell Layout Methodology


Two Versions of (a+b).c


Logic Graph


Consistent Euler Path


Example: x = ab+cd


Properties of Complementary CMOS Gates


Properties of Complementary CMOS Gates


Transistor Sizing


Propagation Delay Analysis - The Switch Model


What is the Value of Ron?


Numerical Examples of Resistances for 1.2mmCMOS


Analysis of Propagation Delay


Design for Worst Case


Influence of Fan-In and Fan-Out on Delay


tp as a function of Fan-In


Fast Complex Gate - Design Techniques


Fast Complex Gate - Design Techniques (2)


Fast Complex Gate - Design Techniques (3)


Fast Complex Gate - Design Techniques (4)


Example: Full Adder


A Revised Adder Circuit


Ratioed Logic


Ratioed Logic


Active Loads


Load Lines of Ratioed Gates


Pseudo-NMOS


Pseudo-NMOS NAND Gate

VDD

GND


Improved Loads


Improved Loads (2)


Example


Pass-Transistor Logic


NMOS-only switch


Solution 1: Transmission Gate


Resistance of Transmission Gate


S

S

Pass-Transistor Based Multiplexer

S

VDD

GND

In1

In2

S


Transmission Gate XOR


Delay in Transmission Gate Networks


Elmore Delay (Chapter 8)


Delay Optimization


Transmission Gate Full Adder


(2) NMOS Only Logic: Level Restoring Transistor


Level Restoring Transistor


Solution 3: Single Transistor Pass Gate with VT=0


Complimentary Pass Transistor Logic


4 Input NAND in CPL


Dynamic Logic


Example


Transient Response


Dynamic 4 Input NAND Gate

VDD

Out

In1

In2

In3

In4

f

GND


Reliability Problems — Charge Leakage


Charge Sharing (redistribution)


Charge Redistribution - Solutions


Clock Feedthrough


Clock Feedthrough and Charge Sharing


Cascading Dynamic Gates


Domino Logic


Domino Logic - Characteristics


np-CMOS


np CMOS Adder


Manchester Carry Chain Adder


CMOS Circuit Styles - Summary


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