Error detection correction
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Error Detection/Correction. Section 1.7 Section 3.9 Bonus Material: Hamming Code. ASCII Code. Communication Control Characters: frame a text message. Format effector: c ontrol layout. ASCII Examples. ASCII A=1000001 ASCII T=1010100. ASCII Code. 10 1 1 001 (Y) 10 0 1 110 (N).

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Error Detection/Correction

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Error detection correction

Error Detection/Correction

Section 1.7

Section 3.9

Bonus Material: Hamming Code


Ascii code

ASCII Code


Error detection correction

Communication

Control

Characters: frame a text message.

Format effector:

control layout


Ascii examples

ASCII Examples

  • ASCII A=1000001

  • ASCII T=1010100


Ascii code1

ASCII Code

1011001 (Y)

1001110 (N)

If the probability of a bit flipping event is 1%,

what is the likely hood that 4 bits are flipped simultaneously?


Parity bit

Parity Bit

  • ASCII characters are stored one per byte (8 bits)

  • The leftmost bit is called the parity bit

  • A parity bit is an extra bit included with a message to make the total number of 1’s either even or odd.


Examples of parity bit

Examples of Parity Bit

  • Even Parity

    • ASCII A=01000001

    • ASCII T=11010100

  • Odd Parity

    • ASCII A=11000001

    • ASCII T=01010100


Signal transmission algorithm

Signal Transmission Algorithm

  • (Even Parity System)

  • A parity bit is generated and attached to the raw data

  • An eight-bit sequence including the parity bit aresent.

  • The parity of each character is checked at the receiving end.

  • If the parity of the received character is not even, then at least one bit has changed value during transmission. The sender must retransmit the signal.


Parity generator

Parity Generator

  • The circuit that generates the parity bit in the transmitter is called a parity generator.

(Truth Table)


Parity checker

Parity Checker

  • The Circuit that checks the parity in the receiver is called a parity checker.


Limitation of parity checking

Limitation of Parity Checking

(1)

(1)


Hardware implementation

Hardware implementation

  • Review of two-terminal XOR/XNOR

  • Three terminal XOR/XNOR

  • Hardware Implementation


Two terminal xor

Two-terminal XOR

  • Equal to 1 if x and y differ in value

  • Alternative description: equal to 1 if an odd number of variables equal to 1

  • Characteristics:


Gate level implementation of xor

Gate Level Implementation of XOR


Alternative implementation of xor

Alternative Implementation of XOR

  • (A’B’)’=A+B


Parity generator1

Parity Generator

  • The circuit that generates the parity bit in the transmitter is called a parity generator.

(Truth Table)


Three terminal xor

Three-Terminal XOR

  • equal to 1 if there is an odd number of variables equal to 1


Four input odd function

Four-Input Odd Function


Parity error check

Parity Error Check

Since , if P=0,

the same circuit can be used

as a 3-bit even parity generator.

zP


Error correction

Error Correction

  • Hamming Code

  • Use check bits to correct error


Raw data

Raw Data

Notation: (bit 1, bit 2, bit 3)

000

001

010

011

100

101

110

111


Add check bits

Add Check Bits

Notation: (bit 1, bit 2, bit 3, bit 4, bit 5, bit 6)

CC0C00

CC0C01

CC0C10

CC0C11

CC1C00

CC1C01

CC1C10

CC1C11


Generate the first check bit

Generate the First Check Bit

0C0C00

0C0C01

1C0C10

1C0C11

1C1C00

1C1C01

0C1C10

0C1C11

Check bit 1 looks at bit 3 and bit 5.

Check bit 1=


Generate the second check bit

Generate the Second Check Bit

000C00

010C01

100C10

110C11

111C00

101C01

011C10

001C11

Check bit 2 looks at bit 3 and bit 6.

Check bit 2=


Generate the third check bit

Generate the third Check Bit

000000

010101

100110

110011

111000

101101

011110

001011

Check bit 4 looks at bit 6 and bit 5.

Check bit 4=


Hamming code

Hamming Code

000000

010101

100110

110011

111000

101101

011110

001011

Blue: Check bits

Black: Data bits


Error in a data bit

Error in a Data Bit

  • Data Bit: 100

  • 111000

  • Error occurs in the 6th bit, we get 111001 instead.

  • Expected check bit 1:. OK

  • Expected check bit 2:. Problem!

  • Expected check bit 4:. Problem!

  • The bad bit is 2+4=6!


Error in the check bit

Error in the Check Bit

  • Data Bit: 100, Check Bit: 110

  • 111000 (No error)

  • Error occurs in the 1thbit, we get 011000instead.

  • Expected check bit 1:. Problem!

  • Expected check bit 2:. OK

  • Expected checkbit 4:. OK

  • The bad bit is bit number 1.


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