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Input Stages. Input Stages - Introduction. Most CMOS inputs have rise/fall time limits Most inputs (FPGAs) also have some hysteresis Typical symbols in specifications t R , t TLH - rise time t F , t THL - fall time t T - transition time Waveform measurement

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Input stages introduction
Input Stages - Introduction

  • Most CMOS inputs have rise/fall time limits

    • Most inputs (FPGAs) also have some hysteresis

  • Typical symbols in specifications

    tR, tTLH - rise time

    tF, tTHL - fall time

    tT - transition time

  • Waveform measurement

    • typically from 10% to 90% but not always

    • sometime parameter measurement method is not specified


Input stages practice
Input Stages - Practice

  • Data sheets may list a parameter for information only and not 100% tested

  • Laboratory devices have shown that not all qualified devices will meet the data sheet

    • One case was when a part was “shrunk”

    • Migration to a faster process

    • Oscillations observed

  • Conservative margins recommended


Input stages termination
Input Stages - Termination

  • Floating CMOS inputs are, in general, 'bad.'

    • Totem-pole currents, oscillations, etc.

  • Some devices offer pull-up/down resistors

    • SX-S only active during power transitions

    • Xilinx resistors controlled by SRAM

    • Care on internal tri-state lines

  • Dedicated Inputs

    • Actel unused inputs were handled by s/w

    • Not true for some SX, SX-S clocks

       Check each case carefully


Input stages termination case study sx s clock pin
Input Stages - TerminationCase Study: SX-S Clock Pin



Input transition times references
Input Transition TimesReferences

  • [1] ACT ™ 1 Field Programmable Gate Arrays, March 1991.

  • [2] ACT 1 and ACT 2 Military FPGAs, April, 1992.

  • [3] ACT ™ 1 Series FPGAs, April 1996.

  • [4] Radiation‑Hardened FPGAs, v3.0, January 2000.

  • [5] ACT ™ 2 Series FPGAs, April 1996.

  • [6] Accelerator Series FPGAs – ACT ™ 3 Family, September, 1997.

  • [7] 54SX Family FPGAs RadTolerant and HiRel, Preliminary V1.5, March 2000.

  • [8] HiRel SX-A Family FPGAs, Advanced v.1, April 2000.

  • [9] RT54SX-S RadTolerant FPGAs for Space Applications, Advanced 0.2, November, 2000.

  • [10] QPRO XQR4000XL Radiation Hardened FPGAs, DS071 (v1.1) June 25, 2000.

  • [11] QPRO™ Virtex™ 2.5V Radiation Hardened FPGAs, DS028 (v1.0) April 25, 2000 Advance Product Specification.

  • [12] Not in data sheet.

  • [13] Configurable Logic Data Book, Atmel, August 1995.

  • [14] AT6000LV, Atmel, October 1999.



Transition time requirements implications pullup resistors
Transition Time RequirementsImplications - Pullup Resistors

  • Often used for tri-state or bi-directional busses

  • Rise time (10% - 90%) =  = 2.2 RC

  • Example

    C = 50 pF

    R = 10 k (keep power levels reasonable)

     = 500 ns

     violates many devices' specifications (see table)


Transition time requirements implications filters and protection circuits
Transition Time RequirementsImplications - Filters and Protection Circuits

  • Often used on signals

    • Elimination of noise

    • ESD protection

    • Etc.

  • RC filters or clamps (high C) can often substantially degrade transition times

  • Consider discrete hysteresis buffers, particularly for clock signals


Bus hold circuit in an fpga

One Bus Hold Circuit

Bus Hold Circuit in an FPGA

Supplies leakage

current only.


Transition time requirements implications interfacing with older logic families
Transition Time RequirementsImplications - Interfacing with older logic families

  • Case Study (1)

    • CD4000B CMOS NOR gate

    • VDD = 5V

    • tT (typ) = 100 ns

  • Case Study (2)

    • CD4050B (used as a level shifter, for example)

    • VDD = 5V

    • tT (max, 25 C) = 160 ns


Transition time requirements implications interfacing with older logic families cont d
Transition Time RequirementsImplications - Interfacing with older logic families (cont'd)

  • Case Study (3) - 54HC00 CMOS NOR gate

    • 5962-8403701VDA, NAND GATE, QUAD 2-INPUT

Test Symbol Test conditions 1/ Limits Unit

-55°C TC+125°C Min Max

unless otherwise specified

Transition time, tTHL, TC = +25C VCC=2.0 75

output rise and tTLH CL = 50 pF VCC=4.5 15 ns

fall 3/ See figure 4 VCC=6.0 13

TC = -55C, -55C VCC=2.0 110

CL = 50 pF VCC=4.5 22 ns

See figure 4 VCC=6.0 19

3/ Transition time (tTLH, tTHL), if not tested, shall be guaranteed to the specified limits in table 1.


Transition time requirements parameter measurement
Transition Time RequirementsParameter Measurement

From: Figure 4,5962-8403701VDA, NAND GATE, QUAD 2-INPUT


Transition time requirements case study rh1020
Transition Time RequirementsCase Study: RH1020

  • Production Parts

    • Input stage was modified for clock upset

  • VCC = +5VDC

  • T=25°C

  • CLKBUF monitored on output

    • Because of design of the buffer, difficult to see effects on the input pin

  • Used a low-impedance signal generator, triangle waveform

  • Commercial specification is tR, tF of 500 ns

    • RH1020 did not meet this specification

    • SMD 5962-90965 does not specify this parameter


Transition time requirements case study rh1020 clkbuf
Transition Time RequirementsCase Study: RH1020 CLKBUF


Transition time requirements rh1020 clkbuf @ v in threshold
Transition Time RequirementsRH1020 CLKBUF @ VIN threshold


Transition time requirements case study rh1020 clkbuf notes
Transition Time RequirementsCase Study: RH1020 CLKBUF Notes

  • Conditions: Room temp; VCC = 5.0 V.

  • Oscillations detected consistently at tR = 360 ns

  • Sporadic output pulses at tR = 300 ns

  • Transition time requirement not symmetric

    • Oscillations detected consistently at tF = 1.5 s

    • Sporadic output pulses observed at tF = 1.0 s


Interfacing voltage margin
Interfacing - Voltage Margin

  • TTL  CMOS

    • Problem with discrete circuits (still seen)

    • Normally not a problem with 5V FPGAs

    • Issue with new FPGAs

      • 0.35 m may only pull up to 3.3 VDC

      • 0.25 m may only pull up to 2.5 VDC

      • Can be issue with parts having a VIH = 70% VDD

      • Ringing can cause false triggering

  • VIL = 0.8V and fast devices are sensitive to ringing on a back plane.


Inputs rt54sx16 t t
Inputs: RT54SX16 tT

RT54SX16 output (bottom trace) with a slow rising input (top trace) which clocks a divide by two counter resulting in a "glitch." The clock input was provided by an HP8110A pulse generator.


Inputs rt54sx16 t t1
Inputs: RT54SX16 tT

RT54SX16 output (bottom trace) with a slow rising input (top trace) which clocks a divide by two counter resulting in a "glitch." The clock input was provided by an HP8110A pulse generator.


Jtag and loss of control
JTAG and Loss of Control

  • Run TCK with TMS=‘1’

    • Guaranteed to return to TEST_LOGIC_RESET state within 5 clocks.

  • Share system clock with TCK

  • JTAG Hit

  • Inputs turn to outputs

    • Clock pin turns to output, clamps system clock

       No TCK, system hangs.


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