Design and Implementation

1. Design and Implementation of a Very Simple CPU Sections 6.1 and 6.2 Stanton Lee

2. 6.1 Specifying a CPU Overview • Determine its applications • Choose an instruction set • Design a state diagram

3. General CPU Cycle Fetch Cycle: Fetch an instruction from memory then go to the decode cycle Decode Cycle: Determine which instruction was fetched then go to the execute cycle Execute Cycle: Execute the instruction then go back to the fetch cycle

4. Generic CPU State Diagram

5. 6.2.1 Specifications • The CPU can access 64 bytes of memory each byte being 8 bits wide • The CPU will output a 6-bit address through pins A[5..0] and read an 8-bit value through pins D[7..0] • There will only be one programmer usable 8-bit accumulator register labeled AC

6. Instruction Set

7. Internal Registers AR: A 6-bit address register that supplies an address to memory via A[5..0] PC: A 6-bit program counter that contains the address of the next instruction to be executed DR: An 8-bit data register that receives instructions and data from memory via D[7..0] IR: A 2-bit instruction register that stores an opcode

8. 6.2.2 Fetching Instructions from Memory First State of the Fetch Cycle • Copy the address in PC to AR • AR will then send the address to memory for reading • FETCH1: AR <-- PC

9. Second State of the Fetch Cycle • The memory will output the requested data to D[7..0] • The CPU will read the data and store it in DR • Increment PC • FETCH2: DR <-- M, PC <-- PC + 1

10. Third State of the Fetch Cycle • Copy the two high-order bits of DR to IR (opcode) • Copy the six low-order bits of DR to AR • These six bits in AR can be used for ADD and AND or ignored for JMP and INC • FETCH3: IR <-- DR[7..6], AR <-- DR[5..0]

11. 6.2.3 Decoding Instructions • Determine which instruction was fetched • Invoke the correct execution routine • For this very simple CPU there are four routines

12. Fetch and Decode Cycles

13. 6.2.4 Executing Instructions The ADD Instruction ADD1: DR <-- M Fetch an operand from memory. Recall that AR already contains an address from FETCH3. ADD2: AC <-- AC + DR Perform the addition and store result in AC Begin the Fetch Cycle again

14. The AND Instruction This is similar to the ADD instruction AND1: DR <-- M Obtain an operand AND2: AC <-- AC ^ DR Perform a logical AND and store Begin the Fetch Cycle again

15. The JMP Instruction JMP1: PC <-- DR[5..0] Simply copy the jump address to PC. The next Fetch Cycle will use that address. Note that because the address was also copied to AR during FETCH3 we can also perform PC <-- AR Begin the Fetch Cycle again

16. The INC Instruction INC1: AC <-- AC + 1 Just add 1 to the accumulator’s value and store the result back into the accumulator Begin the Fetch Cycle again

17. Complete State Diagram

18. 6.2.5 Establishing Data Paths We now design the internal data paths of the CPU to support all possible data transfers Two Approaches • Direct paths between each pair of components that transfer data • A common bus used by all components that need to transfer data

19. Data Transfers AR: AR <-- PC; AR <-- DR[5..0] DR: DR <-- M IR: IR <-- DR[7..6] These components only need to perform data loading

20. Data Transfers (continued) PC: PC <-- PC + 1; PC <-- DR[5..0] AC: AC <-- AC + DR; AC <-- AC ^ DR; AC <-- AC + 1 These components not only load data but they also perform increments

21. Preliminary Register Section Note the tri-state buffers

22. Modify the Design • AR transfers data to memory not to the bus • IR does not supply data to the other registers • AC does not supply data either (unrealistic for a real CPU) • The bus is 8 bits wide but not all transfers use 8 bits. Use bits 5..0 of the bus for AR and PC. Use 7..6 for IR. • The CPU must be able to compute AC + DR and AC ^ DR. Therefore we need an ALU.

23. Final Register Section Note the ALU

24. 6.2.6 Design of an ALU We now consider the implementation of a simple ALU • The two inputs are DR via the bus and AC (direct) • The output goes to AC • Functions • 1. Add the two inputs • 2. Logically AND the two inputs

25. A Very Simple ALU Note the 2-1 MUX and the Control Signal

26. 6.2.7 Designing the Control Unit • Components • Counter: Contains the current state • Decoder: Generates individual signals for each state • Logic Block: Generates control signals for each component

27. Generic Control Unit

28. CPU States Recall that this CPU has a total of 9 states: FETCH1, FETCH2, FETCH3 ADD1, ADD2 AND1, AND2 JMP1 INC1 We will require a 4-bit counter and 4-16 decoder

29. Some Guidelines • Assign FETCH1 to counter value 0 and use the CLR input of the counter to reach this state • Assign sequential states to sequential counter values and use INC on the counter to traverse these states • Assign the first state of each execute routine based on the opcodes and maximum number of states

30. The Mapping Function Some of the execute routines have two states. Therefore we must ensure that their first states are at least two apart. A mapping function that satisfies this is as follows: 1IR[1..0]0

31. Diagram for Control Unit

32. Control Signals We create control signals for the registers PCLOAD = JMP1 PCINC = FETCH2 DRLOAD = FETCH2 OR ADD1 OR AND1 ACLOAD = ADD2 OR AND2 ACINC = INC1 IRLOAD = FETCH3

33. Control Signals (continued) We create control signals for the ALU, the buffers, and M. MEMBUS = FETCH2 OR ADD1 OR AND1 PCBUS = FETCH1 READ = FETCH2 OR ADD1 OR AND1 The ALU has a control input ALUSEL of either 0 or 1 to select the proper function.

34. Control Signal Diagram

35. End of Presentation