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Skew Management of NBTI Impacted Gated Clock Trees

This paper discusses the problem of skew due to negative bias temperature instability (NBTI) in gated clock trees and proposes a solution for minimizing skew after NBTI aging. The proposed solution involves selectively choosing NAND or NOR at the right places in the clock tree to minimize delay difference at sinks.

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Skew Management of NBTI Impacted Gated Clock Trees

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  1. International Symposium on Physical Design 2010 Skew Management of NBTI Impacted Gated Clock Trees Ashutosh Chakraborty and David Z. Pan ECE Department, University of Texas at Austin ashutosh@cerc.utexas.edudpan@cerc.utexas.edu

  2. Outline • Background: Clock Gating & NBTI Effect • Problem: Skew due to NBTI in gated clock • Previous Works • Proposed Solution • Results

  3. Clock Gating • Very popular low power technique • Freeze (“gate”) clock to inactive module • Needs: Signal informing if a module is inactive • Needs: Way to use this signal to freeze clock • Inactivity deduced by checking input permutations • Example: OPCODE for adder? Freeze multiplier clock • RTL simulation and ON/OFF set manipulation helps

  4. Clock Gating (2) • Duration of gating determined by many factors • Gating aggressiveness, input data statistics • How to stop clock signal? • Use NAND/NOR/AND/OR gate • One input: regular clock signal • Other input: Inactivity/Activity signal CLK CLK_OUT Active?

  5. Example Clock Tree FLOPS CLK

  6. Minimize Clock Gating Elements FLOPS 40% CLK 20% 30%

  7. Implementation using NANDs FLOPS GATE: 40% CLK GATE: 20% GATE: 30%

  8. NBTI Effect • Negative Bias Temperature Instability • Occurs when PMOS negatively biased (VGS<0) • Reason: • VGS<0 causes Si-H breaking • Need higher VG to invert channel • Effects: • ∆VTH = +100mV 10 years • 30% increase in inverter delay POLY OXIDE S D [Kumar et. al. DAC 2007] [Alam et. al. 2005 Micro. Reliab.]

  9. NBTI Effect (2) • Proportional to negative bias duration (~tN) • For PMOS in standard cells, • VGS < 0  VG < VDD  Input to cell = logic LOW • Thus, logic LOW feeding a cell causes NBTI • Differing LOW probability  different degradation • Define SP0 = Probability of signal to be LOW • Higher SP0  More NBTI Degradation

  10. Outline • Background: NBTI & Clock Gating • Problem: Skew due to NBTI in gated clock • Previous Works • Proposed Solution • Results

  11. SP0 Difference due to Clock Gating SP0=50% SP0=50% CLK Larger ∆VTH Skew? SP0=50% SP0=50% SP0=35% GATE: 30% Lower ∆VTH • Using NAND gate reduces SP0 at output • Using NOR gate increases SP0 at output • In both cases, ∆VTHmismatch will exist! 11

  12. Problems due to ∆VTH mismatch? • Clock skew can degrade significantly! • Up to 2.5X increase in skew [Chakraborty et al, DATE 2009] • Large variation due to difference in nominal values • Will lead to timing violation and circuit failure

  13. Outline • Background of NBTI & Clock Gating • Problem: Skew due to NBTI in gated clock • Previous Works • Proposed Solution • Results

  14. Previous Works • 2003: US patent 6651230 [John Cohn et. al.] • Essentially overdesign by tightening skew bound. • A limit to which skew constraint can be tightened. • 2009: DATE 09 [Chakraborty et. al.] • First runtime compensation for NBTI in clock trees • At runtime, choose NAND or NOR to drive • Aims to equalize all signal probabilities (of clock nets) • Power Penalty? Routing?

  15. Previous Works (2) CLK Gated at 0 NOR MUX GATE CLK_OUT NAND CLK SELECT Gated at 1 If { GATE = FALSE } CLK_OUT = CLK Else If { SELECT = 0 } CLK_OUT = 0 Else CLK_OUT = 1

  16. Outline • Background of NBTI & Clock Gating • Problem: Skew due to NBTI in gated clock • Previous Works • Proposed Solution • Results

  17. Main Idea • NAND Gate increases SP0 at output • NOR Gate reduces SP0 at output • SP0 impacts delay cell of the cell being driven • Need to reduce delay difference at sinks • Multiple levels of clock gating elements • Can we selectively choose NAND/NOR at the right places, so that even if SP0 is different within the tree, by the time sinks are reached, the delay difference is minimized?

  18. Proposed Solution • At design time (i.e. statically), determine NAND or NOR choice for each gating enabled buffer • Objective: Minimize skew after NBTI aging • Benefits: • No hardware penalty w.r.t. regular clock gating • No glitches due to SELECT signal switch • No extra routing overhead

  19. Our Optimization Flow Symbolic SP0 Propagation SP0 Aware Delay Characterization Symbolic Arrival Time Computation Skew Minimization Formulation Solve

  20. Propagate SP0 in Clock Tree • For gating probability of G & input SP0 of S, output SP0 for NAND or NOR choice:

  21. Example: SP0 Propagation

  22. Delay Characterization • NBTI impacts TRISE. TFALL unchanged • TRISE characterization w.r.t. SP needed • Conducted SPICE simulations to obtain Rise Delay Input SP0

  23. Example [Delay Expression] DINV(0.5) + X2 * DNAND(0.5) + X2’ * DNOR(0.5) + ( X4 * DNAND( 0.72 - X2 * 0.5 ) + X4’ * DNOR( 0.75 - X2 * 0.5 ) )

  24. Can the expressions of Delay and SP become unmanageable as we traverse down the clock tree? Like: X1*X2*X3’*X4*X6’…

  25. Observations • Lemma 1: SP0 of any gate is at most a linear function of Xi. • No multiplication of Xi in SP expression. • Lemma 2: Delay expression is at most a quadratic function of Xi • X1*X2 possible. Not X1*X2*X3 etc. • Thus, delay/SP0 expression remain only quadratic functions of Xi. • If Xi binary, quadratic => linear transformation

  26. ILP Formulation • Minimize: MAX – MIN // Both dummy variables • Subject To: • Arrival Time(Sink i) <= MAX for all i; • Arrival Time(Sink i) >= MIN for all i; • MAX >= 0; • MIN >= 0; • Xi = {0, 1} Max Min

  27. Experimental Setup • Generated balanced clock trees (skew=0) • 9K to 350K sinks. • Buffers at all branching points • Picked 2% of buffers as gating enabled • Assign 20%  70% gating probability • Clock source input SP=0.5 • Spice netlist from 45nm Nangate library • C++ for SP propagation & ILP writing • Mathematica to reduce. CPLEX to solve.

  28. Benchmarks

  29. Outline • Background of NBTI & Clock Gating • Problem: Skew due to NBTI in gated clock • Previous Works • Proposed Solutions • Results

  30. Results • Age the circuit to 10 years • Calculated skew for four cases • Choose NAND/NOR based on our formulation • Choosing all NAND gates • Choosing all NOR gates • Try 10 random assignment, pick best

  31. Results (contd) • Our > Rand > NAND > NOR solution • Significantly tightens the skew budget

  32. Conclusions • Proposed choosing NAND/NOR gating at design time minimize skew degradation. • Optimal (ILP) results show 55% and 120% lower skew than all NAND/all NOR cases. • Random + pick best results reduce 20% and 80% over all NAND/all NOR cases. • Fast. Log(n) binary variables. • Future Works: • ILP is NP complete. Some other formulation. • How ICGs can be handled.

  33. Thank you. Questions?

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