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Automatic Communication Refinement for System Level Design

Automatic Communication Refinement for System Level Design. Samar Abdi, Dongwan Shin and Daniel Gajski Center for Embedded Computer Systems, UC Irvine http://www.cecs.uci.edu. Outline. Main Idea Related work Introductory example Communication refinement Experimental results Impact on SLD.

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Automatic Communication Refinement for System Level Design

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  1. Automatic Communication Refinement for System Level Design Samar Abdi, Dongwan Shin and Daniel Gajski Center for Embedded Computer Systems, UC Irvine http://www.cecs.uci.edu

  2. Outline • Main Idea • Related work • Introductory example • Communication refinement • Experimental results • Impact on SLD

  3. Refinement Possible Design Methodology Evaluate ~6.5K LOC Specification Model Designer Decisions Refinement ~8K LOC Transaction model Evaluate Designer Decisions Communication model ~9K LOC Evaluate Hardware synthesis Interface synthesis Software compilation Implementation model ~15K LOC

  4. Motivation • Rewriting system models is painful • Time consuming • Error prone • Goal : Automatic model rewriting • Extra benefits : • Speedy Design space exploration • Choose a good communication architecture

  5. Related Work • CoWare (Symphony, DAC 1996) • Rendezvous point to point communication with RPC • TIMA (A. Jerraya et al. DAC 2001) • Interface library for parameterized components • Communication using FIFO channels • SystemC Co-centric Studio (http://www.synopsys.com/products/cocentric_studio) • Modeling and Simulation • SCE (http://www.cecs.uci.edu/~cad/sce.html) • Synthesis • Refinement • Evaluation

  6. Transaction level Model Tasks divided amongst components. Point to point data transaction channels. Designer Decisions Arbiter TC1 TC2 TC3 SW HW1 HW2 SW HW1 HW2 IC Decisions and Refinement Generate pin-accurate communication model from transaction level model Communication Model • System Buses • Bus Interfaces • Communication structures ?

  7. Communication Refinement DesignerDecisions Protocol Library Bus Selection Channel Partitioning Interrupt controller type Arbitration policy Arbiter Bus 1 (protocol 1) TC1 TC2 TC3 Bus 2 (protocol 2) SW HW1 HW2 SW HW1 HW2 IC Transaction Level Model Communication Model

  8. Two way blocking communication between components Complex data structures Deterministic behavior Relatively independent WriteDATA ReadDATA Transaction Channel Definition TC DATA Send Recv wait ready ack wait

  9. Read words Interrupt Handler Ready Flag Data Simplification Refinement Example Added during communication refinement System Bus Wires ch Interrupt Bus Master IF Bus Slave IF Writewords Application Layer Application Layer Bit-stream gen. Bit-stream gen. Data Regeneration Send (v) v = Recv( ) SW (Master) HW (Slave)

  10. Bus Transfer SlaveReady = FALSE Communication Style for 2 Statically scheduled components Master Component Slave Component Application Layer Application Layer InterruptHandler SlaveReady == FALSE Interrupt == 0 Notify Interrupt S1 I1 A1 BusAddress != SlaveAddress Interrupt == 1 SlaveReady == TRUE S2 A2 I2 BusAddress == SlaveAddress SlaveReady = TRUE S3 Bus Transfer

  11. Bus Transfer SlaveReady[i] = FALSE Communication Style for Dynamically scheduled master with multiple slaves Master Component Slave Component Application Layer (for variable vi) Interrupt Handler Application Layer SlaveReady [ i ] == FALSE Interrupt == 0 Notify Interrupt S1 I1 A1 Interrupt == 1 SlaveReady [ i ] == TRUE BusAddress != SlaveAddress I2 i = ReadSlaveID() S2 Reserve IOPort A2 BusAddress == SlaveAddress SlaveReady[ i ] = TRUE I2 S3 Bus Transfer Release IOPort

  12. Complete Refinement Algorithm • Derive Connectivity • Instantiate protocol channels • Instantiate application channels • Instantiate communication structures • Slice data • Add synchronization • Master • Slave • Interrupt Handler • For each application channel in master • CodeGen (wait SlaveReady) • If (dynamic scheduling) • CodeGen (req Bus Access) • If (multiple masters) • CodeGen (req Bus; wait gnt) • For each application channel in slave • CodeGen (notify Interrupt) • If (multiple slaves) • CodeGen (wait gnt) • CodeGen (notify address) Bus Comp • For Each bus with numMasters > 1 • Instantiate Arbiter • Make req/gnt port connections • For each master with numSlaves > InterruptPorts • Instantiate Interrupt Controller • Make req/gnt port connections • Depth first traversal over complex data structure • For each Integral type • Convert to bit vector • Slices of data bus width • Generate Code to write sliced words on data bus

  13. Productivity Gain GSM Vocoder models used Experiments done on a 2 GHz Pentium 4 machine using SCE (System-on-Chip Environment) Manual refinement estimated at modifying 10 LOC/person-hr

  14. Quality Analysis • Vocoder Model (1 DSP, 1 HW, 1 DSPBus) • Transaction model size : 7992 LOC • Modified lines of code • Manual refinement : 1141 LOC • Automatic refinement :1299 LOC • Spurious application channel generation • 2 application channels per transaction channel • optimized by identifying reusable application channels • Automatically generated code is more modular and understandable

  15. Conclusions • Automatic generation of communication models • High productivity gain • Applicable to complex communication architectures • Extensive exploration possible • Automatically generated models are maintainable • Improvements to refinement algorithm in the future Visit http://www.cecs.uci.edu/~cad/sce.html

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