ENG6530 Reconfigurable Computing Systems

1. ENG6530Reconfigurable ComputingSystems General Information Handout Fall 2019, September 9th

2. Shawki Areibi Office, Email, Phone • Office: 2335, EXT 53819 • Email: sareibi@uoguelph.ca • Web: http://www.uoguelph.ca/~sareibi • Office Hour: Thursday 2:00 – 3:00 PhD, Waterloo 1995 Research Interests • VLSI Physical Design Automation (CAD/EDA) • Combinatorial Optimization (Heuristics/Meta-heuristics) • Reconfigurable Computing Systems/Embedded Systems RCS - Fall 2019

3. Outline • Staff (TA, Lab Tech) • Lecture Schedule • Course Text and References • Resources and Communication • Assignments, Paper Review, Project • Evaluation • Course contents, Tentative Schedule RCS - Fall 2019

4. Lecture Schedule • Lectures 17:30 – 18:50 (Mon/Wed) • In MACS Room 301 • Note: Lectures might be moved to RICH 2531 • Labs 8:30 – 10:20 AM (Mondays) Rich 1532 RCS - Fall 2019

5. Lab Instructor/Coordinator • Mathew Saunders • Email: msaund05@uoguelph.ca • Richards Building • Room 1506, ext. 53916 RCS - Fall 2019

6. Text Book and References Text Books & References • “Reconfigurable Computing: The Theory and Practice of FPGA-Based Computing”, Edited by S. Hauck, 2008. • “Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications”, by C.Bobda • “Reconfigurable Computing: Accelerating Computation with FPGAs”, by Maya Gokhale • “Computer Organization and Design”, by Patterson and Hennessy • “VHDL for Engineers”, by K. Short, 2009. • “The Designer’s Guide to VHDL”, by Peter Ashenden RCS - Fall 2019

7. Resources & Communication • http://www.uoguelph.ca/~sareibi • Communications • E-mail • ENG6530/ENG3050 Web Pages • Username: engg6530 • Password: rcs2017 RCS - Fall 2019

8. Prerequisites • Digital Design (ENG2410) • Computer Organization (ENG3380) • Basic knowledge of programming languages (C, C++) • Basic Knowledge of Hardware Description Languages (VHDL) • Experience in VLSI Design maybe helpful but not required. RCS - Fall 2019

9. Course Objectives Achieves the following goals: • Gives an overview of the traditional Von Neumann Computer Architecture, its specifications, design and implementations and main drawbacks. Techniques to improve the performance. • Teaches you the internal structure of Programmable Logic in general and Field Programmable Gate Arrays in particular. • Teaches you how digital circuits are designed today using advanced CAD tools and HDLs and high level languages. • Teaches you the basic concepts of Reconfigurable Computing systems (Hardware/Software co-design) • Teaches you when/how to apply Reconfigurable Computing Concepts to design efficient, reliable, robust systems (DSP). • Understand the concept of Run Time Reconfiguration. RCS - Fall 2019

10. Evaluation RCS - Fall 2019

11. Paper Review • Each student (group) is assigned several articles from journal papers/conferences. • Prepare a brief (20 minute) oral presentation of the article or topic (objectives, methods, results, contributions e.t.c.) • A Two page summary giving the citation and the material in the oral presentation must be written and a copy is distributed to each class member. RCS - Fall 2019

12. Paper Review: Topics • Coarse Grained Reconfigurable Arrays • Evolvable Hardware • Floating Point vs. Fixed Point representations • CAD for RCS (High Level Synthesis) • Operating Systems for Reconfigurable Computing • Electronic System Level: A comparison • ASICs vs. FPGAs vs. ASIPs • Run Time Reconfiguration: Challenges • Others … RCS - Fall 2019

13. Research Project • “Graduate Students” will select a topic related to Reconfigurable Computing Systems. • You should conduct an in-depth study covering the problem to be solved and its current status. • Your finding should be documented in a report • Introduction to the problem • Motivation • Background • Literature Review • Methodology • Results • Conclusion RCS - Fall 2019

14. Tentative Schedule • Topic #1, Introduction to RCS • Topic #2, Programmable Logic Devices • Topic #3, CAD for RCS (FPGAs) • Topic #4, VHDL • Topic #5, High Level Languages (Handel-C) • Topic #6, Reconfigurable Processors (ASIPs) • Topic #7, Hardware/Software Co-design • Topic #8, Run Time Reconfigurations • Topic #9, Digital Signal Processing, Tools • Topic #10, Design Exploration Techniques • Topic #11, RCS Applications RCS - Fall 2019

15. What is Reconfigurable Computing? • Mapping algorithms traditionally running on general purpose processors onto reconfigurable platforms to achieve better performance. • Computation using hardware that can adapt at the logic level to solve specific problems • Why is this interesting/important? • Some applications are poorly suited to General microprocessors. • VLSI “explosion” provides increasing resources. • Hardware/Software Co-design is main trend in Embedded Systems. • Accelerate scientific/industrial applications to achieve speedup (Real Time performance is necessary!) RCS - Fall 2019

16. Topic #1: RCS, Introduction • Identify bottlenecks currently found in traditional Von Neumann Architectures. • Learn new techniques to improve performance. • How/Why RCS can fill the gap between ASICs and General Purpose Processors. RCS - Fall 2019

17. Technology Performance Cost Power Flexibility Memory BW I/O BW LOW GPP LOW LOW HIGH HIGH LOW PDSP Medium Medium Medium Medium Medium LOW ASIC HIGH HIGH LOW LOW HIGH HIGH FPGA Med-High LOWt Low-Medium HIGH HIGH HIGH Topic #1, Cont ..: Technology Comparison RCS - Fall 2019

18. Topic #2: Programmable Logic Programmable Or Array Programmable AND array Programmable AND array Programmable Or Array RCS - Fall 2019

19. Topic #2 Cont … : FPGAs • Around the beginning of the 1980s, it became apparent that there was a gap in the digital IC continuum. • At one end, there were programmable devices liks SPLDs and CPLDs, which were highly configurable but could not support large designs. • At the other end of the spectrum were ASICs which can support complex functions but were expensive, time consuming, …. RCS - Fall 2019

20. Topic #3: CAD for Programmable Logic Design Entry Synthesis Logic Optimization Placement Packing LUTs to CLBs Mapping to k-LUT Routing Simulation Configure an FPGA RCS - Fall 2019

21. LE MEM I/O Topic #3: FPGA Design Flow Design Entry/RTL Coding Behavioral or Structural Description of Design Design Specification RTL Simulation • Functional Simulation • Verify Logic Model & Data Flow (No Timing Delays) Synthesis • Translate Design into Device Specific Primitives • Optimization to Meet Required Area & Performance Constraints Place & Route • Map Primitives to Specific Locations inside Target Technology with Reference to Area & • Performance Constraints • Specify Routing Resources to Be Used RCS - Fall 2019

22. Internal Functionality External Interface Topic #4: VHDL circuit A F B Outputs Inputs RCS - Fall 2019

23. Topic #4: Synthesizable VHDL VHDL for Simulation VHDL for Synthesis VHDL for Specification VHDL for Synthesis of Arithmetic Circuits RCS - Fall 2019

24. Topic #5: Managing ComplexityESL RCS - Fall 2019

25. Topic #5: High Level Languages • Take an algorithm written in C. • Generate an efficient hardware design, run it on an FPGA. • Fast design cycle, easy to maintain code. • C programmers should be able to create fast hardware! RCS - Fall 2019

26. Topic #6: ASIPs An ASIP is a stored-memory CPU whose architecture is tailored for a particular set of applications. • The instruction-sets tailored to specific applications or application domains RCS - Fall 2019

27. process (a, b, c) in port a, b; out port c; { read(a); … write(c); } Specification Topic #7: Hardware/Software Co-design Interface Line () { a = … … detach } Partition FPGA Model Capture Synthesize Processor RCS - Fall 2019

28. Topic #8: RTR FPGAs are classified as dynamically reconfigurable if their embedded configuration storage circuitry and corresponding functions can be updated without disturbing the operation of the remaining logic. RCS - Fall 2019

29. Topic #8, Cont ..: Virtual Hardware The concept of Run Time Reconfiguration on FPGAs is similar to the concept of Virtual Memory on Computer Systems. RCS - Fall 2019

30. Topic#9: DSP RCS - Fall 2019

31. Topic #9: DSP, Performance Gap • Algorithmic complexity increases as application demands increase. • In order to process these new algorithms, higher performance signal processing engines are required RCS - Fall 2019

32. Topic #10: Design Exploration • Given an application (software implementation): what is the most appropriate hardware components and communication links that should be used? • The main challenge in DSE arises from the sheer size of the design space that must be explored. • Typically, a large system has millions, if not billions, of possibilities, and so enumerating every point in the design space is prohibitive. RCS - Fall 2019

33. Topic #11: Applications • What applications require Hardware Acceleration? • Image processing, medical applications, real time … • Hardware Accelerators for CAD • Hardware Accelerators for ANNs • Hardware Accelerators for Communication Systems RCS - Fall 2019

34. Satellite Imaging • Satellite imaging used for mapping, environmental studies and defense applications • High-data rate and low-power demands of space require cutting-edge technology such as RC to provide required processing capabilities • Including RC devices in the processing chain will eventually enhance performance c/o US Air Force c/o LANL c/o LANL GMTI processing chain RCS - Fall 2019

35. fMRI and Real-time Human Body Imaging • Technique for determining which parts of the brain are activated by different types of physical sensation or activity – “brain mapping” • High- and low-resolution scans compared using numerous FFTs • Typically post-processed • Much error correction needed due to subject movement • 3D data representation requires a good deal of conventional processing • Studying how RC devices can achieve real-time processing Figures c/o University of Oxford, UK RCS - Fall 2019

36. Questions? RCS - Fall 2019