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COURSE OVERVIEW

School of Computer Studies Principle of Digital Logic CS1105 Brians Komakech Bsc (Comp Eng), MSc (Comp Sci), PhD (Candidate). COURSE OVERVIEW

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COURSE OVERVIEW

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  1. School of Computer StudiesPrinciple of Digital Logic CS1105Brians Komakech Bsc (Comp Eng), MSc (Comp Sci), PhD (Candidate) COURSE OVERVIEW The principle goal of this course is to provide an introduction to digital logic design, which is the basis of computer hardware development. The student, at the completion of this course, should be able to analyze and design logic circuits by understanding formal foundation and selected design techniques OBJECTIVES At the end of the course, students will learn: • The number representation used in today’s digital system and their arithmetic properties and conversion techniques • To analyze and synthesize networks of combinatorial, digital logic elements • To analyze and design digital, clocked sequential circuits • Professional writing and participate in a team work process by performing engineering design using modern computer tools and writing corresponding technical report

  2. CHAPTER ONE: NUMBERREPRESENTATION INTRODUCTION Digital system are built from circuits that process binary digits (1s and 0s), yet very few real life problems are based on binary numbers at all. As a result, a digital system designer must balance/ establish some correspondence between the binary digits and the real life numbers, events and conditions. • Positional Number Representation When dealing with numbers and arithmetic, its convenient to use standard symbols thus (+) for addition and (-) for subtraction 1.1 Unsigned Integers Numbers which are positive only are called Unsigned , and numbers that can also be negative are called Signed. Decimal number system (Base10) consist of digits 0 to 9 and each digit represent a multiple of power of 10. i.e. (8547)=8*103 + 5*102 + 4*101 + 7*100 . we do not normally write the power of 10 because its implied by the position of the digits. This is referred to as Positional Number representation

  3. Binary Number System Base ten is to Decimal as Base two is to binary. In digital circuits, Its not practical to use digits that can assume 10 values, thus we use the binary (base two) which can assume only two values (1 or 0) Bit Nibble = 4 bits Byte = 8 bits Most Significant Digit (MSD) Least Significant Digit (MSD) using 8 bit system, the largest number that can be represented in binary is (11111111)2=(255)10 the smallest number is (00000000)2=(0)10

  4. octal number system Uses eight(8) digits from 0 to 7 in ascending order Rarely used by microprocessors directly. It can be used indirectly through converting to binary Note: eight (8) is a power of two (2) i.e. 8 = 23 It can also be used as an aid in programming Octal 0 1 2 3 4 5 6 7 10 11 12 . . . . . 20 Dec 0 1 2 3 4 5 6 7 8 9 10 . . . , . 16 conversion from decimal to octal Divide repeatedly by eight (8) and record the remainder even if its zero (0) The MSD is the last remainder of the division E.g. Convert 120 decimal to octal Soln: 8 120 R 8 15 0 1 7 12010 = 1708

  5. conversion from binary to octal Divide the number into a group of three digits starting from the LSD Convert each group into its octal equivalent and combine the numbers E.g. convert 1000111011012 to Octal Soln: 1 0 0 0 1 1 1 0 1 1 0 1 4 3 5 5 1000111011012 = 43558 Convert 11011111 to octal Soln: 0 1 1 0 1 1 1 1 1 • 3 7 110111112=3378 Note 0 was added in one group to make it three digits Qtn: why was it added in front of MSD not LSD

  6. Hexadecimal Number System (Base16) Uses digits from 0 to 9 plus the first six (6) English characters of the alphabet It solves the problem of binary number system such that numbers can be easily manipulated especially when large values are involved. Its tedious to deal with large numbers in binary and can result in errors Hexa 0 to 9 A B C D E F Decimal 0 to 9 10 11 12 13 14 15 conversion from hexa to decimal • Multiply the most significant hexa digit by 16 • Add the next most significant digit to the product • Multiply the corresponding sum by 16 • Continue the process until the LSD E.g. Convert 2AC16 to Decimal Soln: Method 1 2 * 16 = 32 32 + A = 42 42 * 16 = 672 672 + C = 684

  7. Soln: Method 2 E.g. Convert 2AC16 to Decimal • Give each hexa digit powers starting from the LSD • Multiply the hexa digit times the base (HexaDigit * BasePower) raised to the corresponding powers. Soln 22 A1 C0 = (2 * 162) + (A * 161) + (C * 160) = (2 * 256) + (10 *16) + ( 12 *16) = 512 +160 + 172 =684 Note: The two methods give the same answer, its upon your discretion to select which methods to use unless otherwise explicitly stated

  8. conversion from hexa to binary Each hexa digit is converted using four (4) digits binary word since 16= 24 The binary results is then combined in their order. Example I: convert 4BA to Binary Soln 4 B A 0100 1011 1010 4BA16 = 0100101110102 Example II: Convert 32AC16 to Binary Soln: 3 2 A C 0011 0010 1010 1100 32AC16 = 00110010101011002 Hexa number system is very convenient for 8 and 16 bit system For 8 bit system, only two (2) hexa digits are required to represent a word and 4 for 16 bit system since each hexa digit contains 4 bits smallest hexa is 0016 = 000000002 Largest hexa is FF16 = 111111112

  9. Conversion from Binary to Hexa Divide the Binary number into four (4) bit digits Convert the division to their hexa equivalent and combine Example convert 10010111101010 to hexa Soln 1 0 0 1 0 1 1 1 1 0 1 0 • 7 A 1001011110102 = 97A16 Example II Convert 1100111000110 to hexa Soln 1 1 0 0 1 1 1 0 0 0 1 1 0 1 9 c 6 11001110001102 = 19C616 To those used to decimal number system, operation in hexadecimal is a bit complex in multiplication, addition, division and subtraction. But all those operations don’t take place inside micro processor, all non binary numbers including hexa, octal, etc are first converted to binary before any operation then converted back to the system as required.

  10. Example: A computer that operates with a terminal that has hexa keyboard and Decimal VDU. When a hexa key is pressed, the number is generated in hexa form then converted to binary, the binary number is then manipulated by the processor, results obtained in binary. the results is then converted to decimal for displays by the VDU

  11. BINARY CODES (BCD) Binary code system generally known as Binary Coded Decimal (BCD) The decimal numbers from 0 to 9 are converted to binary forms using binary digits or bits. Decimal numbers are represented using four (4) binary digits i.e. • 0001 • 0010 • 0011 • 0100 • 0101 • 0110 • 0111 • 1000 • 1001 When decimal numbers have more than one(1) digit, each digit is represented by four binary digits. Example: convert 49810 to BCD 4 9 8 0100 1001 1000 49810 = 0100 1001 1000 in BCD Note: in today's system, the trend is to use either hexa or ASCII outside the processor and binary inside the processor

  12. Comparison of BCD and Binary Its important to realize that BCD is not another number system like Binary, Octal, Decimal and Hexadecimal. Its in fact, the decimal system with each digit encoded in its binary equivalent. its also important to note that BCD is different from straight binary number i.e. the Binary number takes the whole decimal e.g. 137 and represent it in binary while BCD will treat each digit of the decimal individually e.g. 137 is 1 3 7 0001 0011 0101 while 137 can be represented with 8 bits in straight binary, you need 12 bits to represent 137 in BCD. 13710 = 10001001 (Binary) 13710 = 000100110101 (BCD)

  13. AMERICAN STANDARD CODE FOR INFORMATION INTERCHANGE (ASCII) Although the four (4) bit system is sufficient to represent any decimal digit from 0 to 9, additional bits such as the special characters {#, @,?,&} etc cant be represented (look for ASCII table)

  14. PARITY METHOD FOR ERROR DETECTION The movement of Binary data from one location to another is the most frequent operation performed in Digital Systems. E.g. • Transmission of digitized voice over a microwave link • The storage of data in and the retrieval of data from external memory device such as magnetic tape and disk • Transmission of digital data from a computer to a remote computer over telephone lines (i.e. using modem). whenever information is transmitted from one device (transmitter) to another device (the receiver), there is a possibility that errors may occur hence the information received will not be identical to the one that was sent. This can be caused by electrical noise which consist of fluctuation in voltage. much as most digital system are build to be error free, considering that millions of bits are always transmitted, many digital system employ some error detection and correction of errors. The simplest and most common is the parity method. AParity bit is an extra bit that is attached to a code group that is being transferred from one place to another.

  15. The parity bit is either 0 or 1 depending on the number of 1s contained in the code. even parity method, the value of the parity bit is chosen so that the total number of 1s in the group (including the parity bit) is even number. 11000011 Parity bit if the code contains and even number of 1s then a zero is added as the parity bit otherwise if the number of 1s is odd then a 1 is added to make the number even. odd parity method used exactly the same way as except that the parity bit is added in away that the total number of 1s (including the parity bit) is odd 1100001 Parity regardless of whether an even parity or odd parity was used, the parity bit becomes part of the whole code thus the parity bit is treated just like any bit in the code.

  16. Points to note • The parity bit is issued to detect any single bit error that occur during transmission of a code from one location to another. E.g. suppose character A is being transmitted and odd parity is used, the transmitted code would be 11000001.on reception of this code, the receiver checks to see that the number of 1s is odd (including the parity bit), if so the, the receiver will assume that the code was carried correctly. Assuming the receiver gets this code 11000000,it will find that the code has an even number of 1s, it automatically tells the receiver that there must be an error in the code, since presumably the receiver and the transmitter had agreed on odd parity. There is no way however that the receiver can tell which bit is error, since it doesn’t know what the code is to be. it should be apparent that this method would not work if two bits were in error, because two error would not change the oddness or evenness of the number of 1s in the code. in practice, the parity method is used only in situations where the probability of double errors is essentially zero. the transmitter/receiver must agree in advance whether odd or even parity is going to be used.

  17. Predicate Logic Proposition A proposition is statement that either be true of false. We often reduce such statement to a single letter Example L=It is raining R=Sam is a lecturer Questions and explanations are not propositions example What a nice pen! who are you? Negation the negation of a proposition P is the proposition which is false when P is true and true when P is false example r= its is raining ř= it is not raining

  18. The truth table the truth table shows the combination of proposition joined by their operators, they show the relationship the predicates and proposition in true or false form Truth table for negation P -P T F F T We always use letter T to stand for True and F to stand for False. Frequently in computer we often use digits 0 and 1 instead of false and true respectively. Hence the truth table will change to P -P 1 0 0 1 Note: the binary representation of the truth table give aclue as to how the computer handle logic.

  19. PREDICATES These are proposition in that , they can either be true or false, but differ from proposition in that they contain a variable which until specified the trueness or falseness can not be known. e.g. X>10 Predicates and proposition are used as conditions in computer programming and designing. Logic operations Operation, Operand and Operators are the component in logic operation. Proposition may be combined together using a logical operator hence we refer to it as logic operation. A + B = C Operator Operands Example let Q=Musoke is a student R=Musoke is reading Books

  20. P And Q = Musoke is a student And Reading Books AND=Operator P,Q = Operands there are rules that define the AND operation 2 Variable Case 3 Variable case P Q PandQ P Q R P.Q.R 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 The AND is Denoted by ˄ so P and Q is written as P ˄ Q, and is called the AND operation, the logical product or the conjunction (intersection)

  21. THE OR OPERATOR The Or operator is defined in the following truth table. The symbol for OR is ˅, it means the logical sum. There are two types of OR • Inclusive OR • Exclusive OR The exclusive OR does not support both, while the inclusive OR supports the Both cases. Truth table for inclusive OR Pqp ˅ q • 1 1 1 0 1 0 1 1 0 0 0 Truth table for Exclusive OR Pqp ˅ q • 1 0 1 0 1 0 1 1 0 0 0

  22. THE NOT OPERATOR The not operator is the negation of the proposition P is true then not P is false truthtable P -P 1 0 0 1 DESIGN OF A TRUTH TABLE Example: Construct a truth table for S = (p ˄ q) ˅ (p ˄ -q) Solution pq -qp ˄qp ˄-q S 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0

  23. ExampleII Construct the truth table for S = -[(p ˅ -q) ˄ (p ˅ -p) ˄ (-p ˅ -q)] Solution p q -p -q p ˅ -q p ˅ -p -p ˅ -q S 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 1 1 0 Exercise I Construct the truth table for (p ˅ q) ˄ (-r ˄ q) ˅ (-p ˅ -q)

  24. CONDITIONAL STATEMENT many statements especially in computers are of the form if P then Q such statement are called Conditional statements. Its denoted as P Q. and it is read as • P implies Q • P only if Q • P is Sufficient for Q • Q is necessary for P thetruthtableforpq pqpq 1 1 1 1 0 0 0 1 1 0 0 1 from the truth table above, it is only false if p is true and q is false, indicating that a true statement can not indicate a false statement Example

  25. If Kampala is in Uganda then 2+2=5 • If Kampala is in Kenya then 2+2=4 • If Kampala is in Kenya then 2+2=4 • If Kampala is in Kenya then 2+2=5 BICONDITIONAL CONNECTIVE Another common form of statement is P if and only if Q, written as P Iff Q. such statements are called biconditional statements. Thetruthtableforpq pqpq 1 1 1 1 0 0 0 1 0 0 0 1 Example

  26. Kampala is in Uganda if and only if 2+2=5 • Kampala is in Kenya if and only if 2+2=4 • Kampala is in Kenya if and only if 2+2=4 • Kampala is in Kenya if and only if 2+2=5 THE EXCLUSIVE DISJUNCTION The propositional connective ˅ is called the exclusive disjunction p ˅ q, read as p or q but not both. truth table pqp˅q 1 1 0 1 0 1 0 1 1 0 0 0

  27. THE JOINT DENIAL ( ) The propositional connective is called the joint denial, written as p q and read as neither p nor q Thetruthtableforpq pqpq 1 1 0 1 0 0 0 1 0 0 0 1 Example P= he is tall, Q= he is Handsome, write each of the following statements in symbolic form. 1) he is tall and handsome 2) he is tall but not handsome 3) it is false that he is not tall or handsome 4) he is neither tall nor handsome 5) he is tall or he is short and handsome

  28. ExampleII Determine the truth value of the following statements • if 2+3=7 then 4+4=8 Solution Reduce each statement to a single letter Let P=2+3=7 and Q= 4+4=8 P if false (0) and q is true (1) Determine what connective is used If then connective is conditional connective Draw the truth table P q p q 1 1 1 1 0 0 0 1 1 0 0 1 The over all statement is True

  29. Its not true that 2+2=5 if and only if 4+4=10 • Kampala is the capital city of Uganda and Nairobi is the capital city of Tanzania if and only if Masaka is in Northern Uganda

  30. BOOLEAN ALGEBRA P+P=P P.P=P Idempotent law (P+Q)+R=P+(Q+R) (P.Q).R=P.(Q.R) Associative law P+Q=Q+P P.Q=Q.P Commutative law P+(Q.R)=(P+Q).(P+R) P.(Q+R)=(P.Q)+(P.R) Distributive law P+1=1 P+0=P P.1=P Identity law P.0=0

  31. P+-P=1 --P=P P.-P=0 Complementary law -(P.Q)= -P + -Q -(P+Q)= -P . –Q DeMorgan theorem x + x + y= x x. (x + y)= x Absorption Prooffordemorgantheorem pqp.qp.qpqp+q 1 1 1 0 0 0 0 1 0 0 1 0 1 1 0 1 0 1 1 0 1 0 0 0 1 1 1 1

  32. APPLICATION OF THE LAWS Example: Simplify S = (A˄B) ˅(A˄B) ˅ (A˄B) (A˅A) ˄(B˅B)(A ˄ B) A ˄ 1˅(A ˄ B) A˅(A ˄ B) (A˅A) ˄(A˅B) 1 ˄(A˅B) (A˅B) Proof the answer using truth table A B -A -B A ˄ B A ˄ -B -A ˄ -B S A ˅ B 1 1 0 0 1 0 0 11 1 0 0 1 0 1 0 11 0 1 1 0 0 0 0 00 0 0 1 1 0 0 1 11 since the truth table value of the original expression and the calculated are the same, the results is thus correct.

  33. Assignment Simplify the following expression a) A ˅ [B˄(A ˅B)] ˅[A ˅(~A ˅~B)] b) A ˅(A ˅B) ˅(~C ˅B) c) Construct the truth table for [p (~q ˅ r)] ˅ ~[q ˅ (p ~r)]

  34. KARNOUGH MAP It’s a map which represents prepositions in its cells, there are different forms according to the number of variables in the expression to be simplified. A two variable case the variable A,B and their negation can be combined in four ways and by close reference of rows and columns as with a map which can be described as A ~A B AB ~AB ~B A~B ~A~B to represent an expression a one is placed in each of the square for which a term is present e.g. (A˄B) ˅(A ˄ ~B) =A Soln A ~A B 1 ~B 1

  35. UsingAlgebra ( A.B) + (A.~B) (A+A) . (B.~B) A.1 A three (3) Variable case the variable A, B and C and their negations can be combined in eight ways by a cross reference of rows and columns. A ~A C ACB ~ACB A~CB ~A~CB B ~C A~C~B ~A~B~C C AC~B ~A~BC ~B

  36. Logic Circuits Gates are the fundamental component in digital logic circuits. Gates are constructed from elementary electronic components: a transistors and resistors. Logic circuits require a power source and represent binary values by two distinct voltage levels. Logic diagrams often omit the supply voltages and focus There are three fundamental gates that illustrate the use of these components. Brians Komakech - Cavendish University

  37. AND - OR -NOT • The three gates shown below implement the Boolean NOT, NAND, and NOR functions. NOT gates are commonly called inverters • All logic circuits can be constructed from the above subset of just 3 gates (other subsets are sufficient as well).

  38. Logic Circuit Design Steps 1 Reduce statements to single letter representation 2 Represent outputs in terms of inputs 3 Draw the truth tables 4 Get the sum of products 5 Reduce the sum of products using karnough maps or algebra 6 Construct the logic circuits Example Design a parity detector which produces a warning signal when it receives two inputs of un even parity? Brians Komakech - Cavendish University

  39. NAND-NOR Although all logic circuits can be built by using the combination of just AND-OR and NOT, additional gates such as NAND NOR are often used Example Convert the sum of half adder from AND-OR-NOT format to NAND-NOR format Soln Apply Demorgan repeatedly until desired results is obtained.

  40. Integrated Circuits (IC) An integrated circuit is a collection of gates integrated into a single chip. The number of gates on a chip is used for classification: SSI - small scale integration - 1-10 gates MSI - medium scale integration - 10-100 gates LSI - large scale integration - 100-100,000 gates VLSI - very large scale integration - over 100,000 gates Typical SSI chips provide 4-6 simple gates in a single dual-inline package (DIP). Pins protruding from the DIP provide connections to the input and output lines of the internal gates as well as the necessary power connections. Brians Komakech - Cavendish University

  41. Combinational Circuits These SSI chips can be combined to build combinational circuits. Combinational circuits are implementations of truth tables or Boolean functions. Their output is uniquely determined by their current input values. There are standard combinational circuits that are pre-built and provided in a single chip. Assignment 1 Distinguish between Multiplexers, Decoders and Comparators Brians Komakech - Cavendish University

  42. Half Adder (HA) Part of ALU that performs addition of two bit inputs X and Y produces output of sum (s) and carry (c) Truth table S=~xy+x~y C=xy Brians Komakech - Cavendish University

  43. Full Adder (FA) A full adder has three inputs to accommodate a carry in to the current bit position. It can be constructed by connecting two half-adders, the carry out is 1 when there is a carry from either of the two stages (there cannot be 2 carries).. truth table Brians Komakech - Cavendish University

  44. Memory limiting factor in a computer’s performance has been memory access time - Memory speed has been slow compared to the speed of the processor - A process could be bottlenecked by the memory system’s inability to “keep up” with the processor Goal To study the development of an effective memory organization that supports the processing power of the CPU - General memory organization and performance - Internal” memory components and their use - External” memory components and their use Brians Komakech - Cavendish University

  45. Terminology Capacity: the amount of information that can be contained in a memory unit - usually in terms of words or bytes. Word: the natural unit of organization in the memory, typically the number of bits used to represent a number. Addressable unit: the fundamental data element size that can be addressed in the memory -- typically either the word size or individual bytes. Unit of transfer: The number of data elements transferred at a time —usually bits in main memory and blocks in secondary memory Brians Komakech - Cavendish University

  46. Transfer rate: Rate at which data is transferred to/from the memory device. Access time: RAM. the time to address the unit and perform the transfer Non-RAM - the time to position the R/W head over the desired location. Memory cycle time: Access time plus any other time required before a second access can be started. Access technique: how memory contents are accessed. Random access: Each location has a unique physical address Locations can be accessed in any order and all access times are the same. What we term ‘RAM” is more aptly called read/write memory since this access technique also applies to ROMs as well. E g Main memory Brians Komakech - Cavendish University

  47. Sequential access: Data does not have a unique address Must read all data items in sequence until the desired item is found Access times are highly variable e.g. tape drive units Direct access: Data items have unique addresses Access is done using a combination of moving to a general memory “area” followed by a sequential access to reach the desired data item. e.g. Disk drives Brians Komakech - Cavendish University

  48. Associative access A variation of random access memory Data items are accessed based on their contents rather than their actual location Search all data items in parallel for a match to a given search pattern All memory locations searched in parallel without regard to the size of the memory. Extremely fast for large memory sizes Cost per bit is 5-10 times that of a “normal” RAM cell Example: some cache memory units Brians Komakech - Cavendish University

  49. Memory Hierarchy Major design objective of any memory system. To provide adequate storage capacity at An acceptable level of performance At a reasonable cost Four interrelated ways to meet this goal. Use a hierarchy of storage devices Develop automatic space allocation methods for efficient use of the memory. Through the use of virtual memory techniques, free the user from memory management tasks. Design the memory and its related interconnection structure so that the processor can operate at or near its maximum rate. Brians Komakech - Cavendish University

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