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Introduction to Controlling the Output Power of a Transistor Stage

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A load network will be designed to maximize the output power obtainable from the Mitsubishi MGF0909A power transistor. The gain associated with maximum power is high enough not to be a concern in this case.

Two solutions to the matching problem will be considered. The network selected will be expanded to allow for feeding the required dc to the drain of the transistor. Care will be taken to model the effects of the high Q capacitors added accurately.

Changes will also be made to the matching network to reduce the expected discontinuity effects and the network will be optimized to restore the power performance.

The performance around the power contour targeted is tabulated at 2.075GHz. The optimum point on the contour is high-lighted and can be changed at this point.

The lines are used to model the phase shift through the capacitor and should not be present physically. The line commands will be modified as required in the Text View.

The load network of the power amplifier was designed in this example. The synthesized network was extended to allow for the drain biasing of the transistor and the expected step discontinuity effects were reduced.

The input network will be designed in the final phase of this power amplifier example .