introduction to controlling the output power of a transistor stage
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Introduction to Controlling the Output Power of a Transistor Stage. A load network will be designed to maximize the output power obtainable from the Mitsubishi MGF0909A power transistor. The gain associated with maximum power is high enough not to be a concern in this case.

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introduction to controlling the output power of a transistor stage
Introduction to Controlling the Output Power of a Transistor Stage

A load network will be designed to maximize the output power obtainable from the Mitsubishi MGF0909A power transistor. The gain associated with maximum power is high enough not to be a concern in this case.

Two solutions to the matching problem will be considered. The network selected will be expanded to allow for feeding the required dc to the drain of the transistor. Care will be taken to model the effects of the high Q capacitors added accurately.

Changes will also be made to the matching network to reduce the expected discontinuity effects and the network will be optimized to restore the power performance.

slide3
The CIL Command is selected on the left (Synthesis Toolbar) to control the output power of the transistor.
slide9
The actual output power and the operating power gain are of interest. Power contours will be generated.
slide13
The maximum power is targeted. Additional contours can be displayed at 1dB and 2dB down from the optimum.
slide14

The performance around the power contour targeted is tabulated at 2.075GHz. The optimum point on the contour is high-lighted and can be changed at this point.

slide15
The terminations to be presented by the matching network in order to realize the power targeted are tabulated here.
slide16
The Display Impedance Radio Button was selected to list the impedance required for maximum output power (the power targeted).
slide19
The Impedance-Matching Module has been activated. The problem will be solved with a non-commensurate microstrip network.
slide20
The Distributed Network Wizard will be launched to set the constraints on the microstrip networks to be synthesized.
slide88

The lines are used to model the phase shift through the capacitor and should not be present physically. The line commands will be modified as required in the Text View.

slide95
The effect of the added components on the performance is evaluated. The output power has not changed much.
slide96
The shorted stub will be replaced with a line shorted to ground at RF frequencies with a capacitor (drain biasing).
slide98
The relevant shorted stub is selected on the schematic too. A shunt block will be inserted in parallel with this stub.
slide100
Because the first element of the shunt block is selected the new element can be inserted to its right or to the right of the block.
the newly inserted line was edited to be the same as the original shorted stub to be removed
The newly inserted line was edited to be the same as the original shorted stub (to be removed).
slide110
DC can now be fed to the drain via the inserted shunt block. The original inductor will now be deleted.
extra lines will again be inserted on both sides of the capacitor to model the phase shift effect
Extra lines will again be inserted on both sides of the capacitor to model the phase shift effect.
slide118
Scrolling of the view will be turned off. This will allow centering of the view around the selected component.
slide131
Another shunt block will be inserted in the schematic to allow for feeding in the dc to the right of the selected line.
slide133
Two position options are provided when the insert command is activated on the first element of a shunt block.
slide142
The performance is analyzed with the changes made. The components added did not change the output power significantly.
slide144
The length of the dc line is changed slightly to verify that the circuit performance is not sensitive to the length used.
slide152
A line is bent from its output side towards its input side (marked with the triangle). The line will be bent anti-clockwise.
if relative position of the bend is specified as 0 65 further away from the output side of the line
If relative position of the bend is specified as 0.65 (further away from the output side of the line).
slide161
The Analysis Options for the circuit are stored in the circuit file. The Save Command is used to save the change in these settings.
lines will be inserted on both sides of the selected line in order to reduce the step transitions
Lines will be inserted on both sides of the selected line in order to reduce the step transitions.
the performance after the optimization is displayed note that the output power has been restored
The performance after the optimization is displayed. Note that the output power has been restored.
last phase of this example
Last Phase of this Example

The load network of the power amplifier was designed in this example. The synthesized network was extended to allow for the drain biasing of the transistor and the expected step discontinuity effects were reduced.

The input network will be designed in the final phase of this power amplifier example .

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