Introduction to controlling the output power of a transistor stage
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Introduction to Controlling the Output Power of a Transistor Stage. A load network will be designed to maximize the output power obtainable from the Mitsubishi MGF0909A power transistor. The gain associated with maximum power is high enough not to be a concern in this case.

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Introduction to controlling the output power of a transistor stage
Introduction to Controlling the Output Power of a Transistor Stage

A load network will be designed to maximize the output power obtainable from the Mitsubishi MGF0909A power transistor. The gain associated with maximum power is high enough not to be a concern in this case.

Two solutions to the matching problem will be considered. The network selected will be expanded to allow for feeding the required dc to the drain of the transistor. Care will be taken to model the effects of the high Q capacitors added accurately.

Changes will also be made to the matching network to reduce the expected discontinuity effects and the network will be optimized to restore the power performance.



The CIL Command is selected on the left (Synthesis Toolbar) to control the output power of the transistor.






The s parameter normalization resistance can be changed here
The position shown.S-parameter normalization resistance can be changed here.


The actual output power and the operating power gain are of interest. Power contours will be generated.


The power targeted must be specified on this page
The power targeted must be specified on this page interest. Power contours will be generated.


The display contours command has been selected
The Display Contours Command has been selected. interest. Power contours will be generated.



The maximum power is targeted. Additional contours can be displayed at 1dB and 2dB down from the optimum.


The performance around the power contour targeted is tabulated at 2.075GHz. The optimum point on the contour is high-lighted and can be changed at this point.


The terminations to be presented by the matching network in order to realize the power targeted are tabulated here.


The Display Impedance Radio Button was selected to list the impedance required for maximum output power (the power targeted).




The Impedance-Matching Module has been activated. The problem will be solved with a non-commensurate microstrip network.


The Distributed Network Wizard will be launched to set the constraints on the microstrip networks to be synthesized.













The steps of the wizard have been completed
The steps of the wizard have been completed. with the specifications made.

















































The first line was added
The first line was added. phase shift associated with it.


The second line was added
The second line was added. phase shift associated with it.








The lines are used to model the phase shift through the capacitor and should not be present physically. The line commands will be modified as required in the Text View.








The effect of the added components on the performance is evaluated. The output power has not changed much.


The shorted stub will be replaced with a line shorted to ground at RF frequencies with a capacitor (drain biasing).


Topology changes must be made in a schematic view
Topology changes must be made in a Schematic View. ground at RF frequencies with a capacitor (drain biasing).


The relevant shorted stub is selected on the schematic too. A shunt block will be inserted in parallel with this stub.


A line will be inserted to the right of the inductor
A line will be inserted to the right of the inductor. A shunt block will be inserted in parallel with this stub.


Because the first element of the shunt block is selected the new element can be inserted to its right or to the right of the block.


The newly inserted line was edited to be the same as the original shorted stub to be removed
The newly inserted line was edited to be the same as the original shorted stub (to be removed).








The 0 1pf capacitor will be deleted
The 0.1pF capacitor will be deleted. a shunt block is selected.



DC can now be fed to the drain via the inserted shunt block. The original inductor will now be deleted.


The modified schematic will be saved
The modified schematic will be saved. The original inductor will now be deleted.


The artwork after the modifications made
The artwork after the modifications made. The original inductor will now be deleted.


Extra lines will again be inserted on both sides of the capacitor to model the phase shift effect
Extra lines will again be inserted on both sides of the capacitor to model the phase shift effect.


The first line was inserted
The first line was inserted. capacitor to model the phase shift effect.


The second line was inserted
The second line was inserted. capacitor to model the phase shift effect.


The circuit should be saved often
The circuit should be saved often. capacitor to model the phase shift effect.


The pad lengths will be edited in the artwork view
The pad lengths will be edited in the Artwork View. capacitor to model the phase shift effect.


Scrolling of the view will be turned off. This will allow centering of the view around the selected component.














Another shunt block will be inserted in the schematic to allow for feeding in the dc to the right of the selected line.



Two position options are provided when the insert command is activated on the first element of a shunt block.


The series inductor will be deleted
The series inductor will be deleted. activated on the first element of a shunt block.


The option to delete the element or the block is provided
The option to delete the element or the block is provided. activated on the first element of a shunt block.


The value of the 0 1pf capacitor will be changed to 22pf
The value of the 0.1pF capacitor will be changed to 22pF. activated on the first element of a shunt block.







The performance is analyzed with the changes made. The components added did not change the output power significantly.


The summary table will be removed
The Summary Table will be removed. components added did not change the output power significantly.


The length of the dc line is changed slightly to verify that the circuit performance is not sensitive to the length used.


The performance is checked with the modification
The performance is checked with the modification. that the circuit performance is not sensitive to the length used.


The changes made will be saved1
The changes made will be saved. that the circuit performance is not sensitive to the length used.


The artwork of the circuit
The artwork of the circuit. that the circuit performance is not sensitive to the length used.


The gap size of the capacitor will be edited
The gap size of the capacitor will be edited. that the circuit performance is not sensitive to the length used.


The gap size of the capacitor has been adjusted
The gap size of the capacitor has been adjusted. that the circuit performance is not sensitive to the length used.




A line is bent from its output side towards its input side (marked with the triangle). The line will be bent anti-clockwise.



If relative position of the bend is specified as 0 65 further away from the output side of the line
If relative position of the bend is specified as 0.65 (further away from the output side of the line).


The length of the output line will be increased
The length of the output line will be increased. (further away from the output side of the line).


The performance of the amplifier is analyzed again
The performance of the amplifier is analyzed again. (further away from the output side of the line).






The Analysis Options for the circuit are stored in the circuit file. The Save Command is used to save the change in these settings.


The dimensions of the capacitive line are viewed
The dimensions of the capacitive line are viewed. circuit file. The Save Command is used to save the change in these settings.


Lines will be inserted on both sides of the selected line in order to reduce the step transitions
Lines will be inserted on both sides of the selected line in order to reduce the step transitions.


The line of interest is also selected on the schematic
The line of interest is also selected on the schematic. in order to reduce the step transitions.








































The option to update the circuit with the optimized element values is provided after optimization
The option to update the circuit with the optimized element values is provided after optimization.


The changes will be saved
The changes will be saved. values is provided after optimization.


The performance after the optimization is displayed note that the output power has been restored
The performance after the optimization is displayed. Note that the output power has been restored.


The artwork of the optimized output network is displayed
The artwork of the optimized output network is displayed. that the output power has been restored.


Last phase of this example
Last Phase of this Example that the output power has been restored.

The load network of the power amplifier was designed in this example. The synthesized network was extended to allow for the drain biasing of the transistor and the expected step discontinuity effects were reduced.

The input network will be designed in the final phase of this power amplifier example .


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