Implementation of parity bit generator/checker. - Kavyashree Pilar. Project proposal. Implemen t ation of parity bit generator and checker circuit. Project d eliverables : Schematic Worst case timing analysis Power and thermal analysis
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Implementation of parity bit generator/checker
Implementation of parity bit generator and checker circuit.
Worst case timing analysis
Power and thermal analysis
Hardware implementation and functionality verification.
74AC164 : 8 bit shift register
74AC86 : Quad 2-input ExOR gate
PCB Board Specification:
Standard board : 10mils thick with copper routing layers on top and bottom.
F_knee = 166.66MHz
AC coupling capacitor value = 100pF
Length of rising edge(L) = 21.347”
L/4 = 5.3368”
Longest trace length ~ 5”
No termination required
Each output drives 2 ExOR gate inputs
Q5 and Q6 drive one more ExOR gate
CPD= 150pF, Ci = 10pF, assume f = 36MHz
Pd = 234.3mW
θJA = 700C/W
Junction temperature = 51.4010 C
MTBF is very good – No cooling required.
PCB design using OrCAD capture/CIS and PCB editor.
Issues faced and solutions:
ORCAD capture – schematic done V6.6 demo version can not be modified with V6.3.
Demo version can handle only upto 60 components.
The following command can be used on command prompt can be used when netlist generation via GUI fails:
C:\Cadence\SPB_16.3\tools\capture\pstswp -pst -d "<filename>.DSN" -n "allegro" -c "C:\Cadence\SPB_16.3\tools\capture\allegro.cfg"
CD74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE - Texas Instruments
CD54/74AC164, CD54/74ACT164 8-Bit Serial-In/Parallel-Out Shift Register - Texas Instruments
Thermal conductivity information
PCB Design :
“Capture CIS Tutorial” - EkaratLaohavaleeson
“Layout Editor Tutorial” - Jordan Bisasky