leon.vhd

1. leon.vhd mcore0 : (mcore) SDRAM mctrl0 : (mctrl) proc0 : (proc) Processor and Cache cntrl addr (dus_mem) data Network_contol_interface reset0 : (rstgen) Reset generator Gig_Eth Note: rest and clk signals not shown !!!

2. Network_contol_interface leon.vhd mcore0 : (mcore) mctrl0 : (mctrl) FPX SDRAM Controller ????? SDRAM cntrl addr data Network_control_interface Control packet(R/W SDRAM Debug interface (dus_mem) Gig_Eth Note: rest and clk signals not shown !!!

3. mctrl0 : (mctrl) cntrl SDRAM addr data sdctrl : (sdmctrl) Note: rest and clk signals not shown !!!

4. Vhdl record definitions memo : memory_out_type { address(28) : data(32) : ramsn(3) : ramoen(3) : iosn(1) : romsn(2) : oen(1) : writen(1) : wrn(4) : bdrive(1) : read(1) : } memi : memory_in_type { data(32) : brdyn(1) : bexcn(1) : writen(1) : wrn(4) : }

5. Vhdl record definitions mctrlo : mctrl_out_type { } sdo : sdram_out_type { } sdi : sdram_in_type { }

6. Vhdl record definitions (cont) ahbsi : ahb_slv_in_type { } ahbso : ahb_slv_out_type { } aphi : apb_slv_in_type { } apho : apb_slv_out_type { }

7. Vhdl record definitions (cont) pioo : pio_out_type { } wpo : wprot_out_type { } ahbmi : ahb_mst_in_vector { } ahbmo : ahb_mst_out_vector { }

8. Vhdl record definitions (debug signal) dmo : dsumem_out_type { } dmi : dsumem_int_type { } dsi : dsuif_in_type { } dsuo : dsu_out_type { }