New Metrics in Voltage Partitioning with Application to Floorplanning

1. New Metrics in Voltage Partitioning with Application to Floorplanning Shiyan Hu Dept of Electrical and Computer Engineering Michigan Technological University 1

2. 3 1 2 4 Conclusion Introduction The Algorithm Experimental Results Peak Power Density Driven Voltage Partitioning 2

3. Thermal Impacts Timing, Leakage and Reliability J.-L. Tsai, C. C.-P. Chen, G. Chen, B. Goplen, H. Qian, Y. Zhan, S.-M. Kang, D.-F. Wong, and S. S. Sapatnekar, “Temperature-Aware Placement for SOCs,” Proceedings of the IEEE, Vol. 94, No. 8, pp. 1502 - 1518, August 2006. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. “Temperature-Aware Microarchitecture.” In Proceedings of the 30th International Symposium on Computer Architecture, pp. 2-13, June 2003. W.L. Hung, G.M. Link, Y. Xie, Vijavkrishnan, N, Drhanwadaf, and J. Conner, “Temperature-aware voltage islands architecting in system-on-chip design”, ICCD, 2005. J. Cong, G. Luo, J. Wei, and Y. Zhang, "Thermal-Aware 3D IC Placement via Transformation ," ASP-DAC, 2007. Y. Zhan, S. V. Kumar, and S. S. Sapatnekar, “Thermally-Aware Design,” Foundations and Trends in Electronic Design Automation, Vol. 2, No. 3, pp. 255 – 370, 2008. J.-L. Tsai, C. C.-P. Chen, G. Chen, B. Goplen, H. Qian, Y. Zhan, S.-M. Kang, D.-F. Wong, and S. S. Sapatnekar, “Temperature-Aware Placement for SOCs,” Proceedings of the IEEE, Vol. 94, No. 8, pp. 1502 - 1518, August 2006. 3

4. Power Density Impacts Thermal • Power density driven floorplanning can efficiently impacts temperature. • Maximum (peak) power density is a first-order estimation of maximum temperature, hotspots. • Existing works in voltage partitioning use power as a first-order estimation. Compact Resistive Thermal Model Temperature = Power Rt = Power  ɛ/(k  Area) = (ɛ/k) PowerDensity, where ɛ is the thickness of the chip and k is the thermal conductivity of the material. Yongkui Han and Israel Koren, “Simulated Annealing Based temperature Aware Floorplanning”, Journal of Low Power Electronics, Vol. 3,1-15, 2007 4

5. [1] Z. Gu, Y. Yang, J. Wang, R. Dick, and L. Shang, “Taphs: thermal-aware unified physical-level and high-level synthesis,” ASPDAC, pp. 879 – 885, 2006. [2] H.-Y. Liu, W.-P. Lee, and Y.-W. Chang, “A provably good approximation algorithm for power optimization using multiple supply voltages,” DAC, pp. 887 – 890, 2007. [3] Tao Lin, Sheqin Dong, Bei Yu, Song Chen, and Satoshi Goto: A revisit to voltage partitioning problem. GLSVLSI, pp.115 –118, 2010. Previous Voltage Partitioning Works Do Not Consider Peak Power Density 5

6. Dynamic Power Nehalem 130 100 P6 P5 10 486 286 8086 Power (Watts) 386 8085 1 8080 8008 4004 0.1 Technology node 1971 1974 1978 1985 1993 2008 Year 6

7. Voltage Partitioning Impacts Power Density • Voltage partitioning/assignment enables voltage island t4 t1 t2 t5 t1 t2 t5 t3 t4 t3 1.2 0.8 1.2 0.8 7

8. Two Partitioning Solutions on GSRC n100 8

9. Peak Power Density Power density of an FU is its dynamic power on unit area. Peak power density of a partition T is the maximum power density over all FUs in T 9

10. A Partitioning Example Suppose that we partition them into two groups: 10

11. Problem Formulation Voltage Partitioning For Peak Power Density Minimization Problem: Given m voltage levels, a set T of n functional units, the capacitance, area and minimum voltage of each functional unit, the problem is to partition T into at most m groups, such that the peak power density over all groups is minimized. 11

12. Main Idea Guess Peak Power Density Achievable? No Yes Decrease Guessed Value Increase Guessed Value 12

13. Achievable? CORE Decision Problem: Given a peak power density target P and a number m, whether there is a partitioning solution such that the peak power density over all partitions is no greater than P and the number of partitions is no greater than m? 13

14. Problem Mapping V’ t2 t1 t4 t6 t5 t3 C’ 14

15. CORE Equal power density curve from guessed value V’ C’ 15

16. Optimality: Using Minimum Number of Partitions Equal power density curve V’ Characteristic voltage node C’ # characteristic voltage nodes gives lower bound of minimum # of partitions # of partitions in our CORE solution = # characteristic voltage nodes 16

17. Speedup Guess Peak Power Density • To find highest V’ in remaining nodes • Half-space cut-tree in O(log n) time. • Stop when already form m partitions • Note that CORE returns whether >m partitions or <= m partitions are needed to achieve power density P. Achievable? No Yes Decrease Guessed Value Increase Guessed Value 17

18. Half-Space Cut Tree 5 (y1 , y7) V’ 1 2 7 4 7 (y1, y4) (y6 , y7) 3 5 1 2 4 6 8 8 (-, y1) 6 (- , y6) (- , y8) (y3, y4) 3 C’ (-, y3) In (v’l, v’r), v’l records the maximum v’ from it’s left subtree and v’r records the maximum v’ from its right subtree and the node itself. 18

19. Using Half-Space Cut Tree 5 (y1 , y7) V’ 2 7 1 • If the node’s left subtree is cut but the node itself is not cut, it’s v’l will be of no use and its v’r will be used to update tmpvmax. • If the node is cut (so its left subtree must also be cut), its v’l and v’r will be of no use. • If a node’s left subtree is not cut, both of its v’l and v’r will be used to update tmpvmax (y1, y4) (y6 , y7) 4 7 1 3 4 6 8 5 (-, y1) (- , y6) (- , y8) (y3, y4) 2 8 6 3 C’ (-, y3) tmpvmax= max (y4, y7) y4 y4 max (y4, 0) 0 19

20. CORE Theorem Theorem 1: Given a set of T with n functional units, a power density target P and a number m, deciding whether there is a partitioning solution such that the peak power density over all partitions is no greater than P and the number of partitions is no greater than m can be performed in O(mlog n) time, excluding the O(nlog n) preprocessing time. 20

21. Simple Binary Search Guess Peak Power Density V’ Achievable? upper bound No Yes lower bound Decrease Guessed Value Increase Guessed Value C’ 21

22. A Better Binary Search First sort all O(n2) power density curves and perform binary search on them using CORE. V’ CORE Query >m <=m upper bound The searched power density will be the new lower bound < =m The searched power density will be the new upper bound > m lower bound C’ 22

23. Algorithmic Flow Preprocessing Smart Binary Search In each iteration, compute partitions incrementally and instead of binary search on power density we perform binary search on C’ to compute/fix each partition CORE QUERY OPT 23

24. To Fix First Partition Input: m = 3 5 partitions > m lower bound = ki V’ power density =ki+1 power density =ki It is not achievable 2 partitions < m upper bound = ki+1 1 3 partitions = m {1,2,3,4,5} are in the 1st partition The 1st partition can be fixed This is a candidate solution. 4 2 Can it be achievable? 5 3 New upper bound power density=ki+2 C’ Binary search on C’ 24

25. To Fix Second Partition The 1st partition can be fixed 5 partitions > M V’ 3 partitions <= M This is a candidate solution. 1 4 partitions > M 4 2 5 3 C’ Binary search on C’ 25

26. To Fix Second Partition The 1st partition can be fixed 5 partitions > M V’ 3 partitions <= M 1 4 partitions > M The 2nd partition can be fixed 4 2 5 3 C’ Binary search on C’ 26

27. V’ 1 Recursion Tree 4 2 5 3 V’ V’ V’ M = 3 C’ Binary search on C’ 1 1 1 Height = m 4 4 4 2 2 2 3 5 5 5 5 3 3 3 3 4 To be continue … C’ C’ C’ Binary search on C’ Binary search on C’ Binary search on C’ 27

28. Main Theorem Theorem 2: Given a set of n functional units and m voltage levels, the minimum peak power density voltage partitioning solution can be computed in time. Preprocessing Core: mlogn # calls to core: mlogn 28

29. Experimental Setup • The algorithm is tested on a machine with a quad-core CPU at 2.4 GHz and 8G memory. • Randomly generated testcases whose sizes are from 100K to 1M. • Compare to a natural greedy algorithm which iteratively assigns a functional unit to the partition such that the power density can be minimized in this iteration. 29

30. Experimental Results P.P.D. refers to peak power density 30

31. P.P.D. Comparison Peak Power Density Testcase Size 31

32. Runtime Comparison CPU (s) Testcase Size 32

33. The Testcase w/ 100k FUs # of Partitions # of Partitions 33

34. Floorplanning Results on GSRC Benchmark Circuits W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, “Voltage island partitioning and floorplanning under timing constraints,” IEEE Trans. Computer-Aided Design, Vol. 28, No. 5, pp. 690--702, May 2009. 34

35. Conclusion for Peak Power Density Driven Voltage Partitioning • This work proposes an efficient optimal voltage partitioning algorithm for peak power density minimization, • The algorithm runs in O(nlogn + m2log2n) time, where n refers to the number of functional units and m refers to the number of partitions. • Experimental results on large testcases demonstrate that the proposed algorithm can achieve large amount of (about 9.7 X) reduction in peak power density compare to a natural greedy algorithm. • Our algorithm needs only 14.15 seconds to optimize 1M functional units. • Future work seeks to perform peak power density driven thermal aware floorplanning. 35

36. 1 2 3 4 Problem Formulation NP-Complete Proof The Algorithm Experimental Result Peak Power Driven Voltage Partitioning 5 Conclusion 36

37. Peak Power • Voltage partitioning is to partition blocks into groups • Power of a group T • Peak power of a partitioning solution is the largest power among all groups where 37

38. An Example 38

39. Power Balancing Why balancing? t3 t3 t1 t1 t2 t2 t5 t4 Power Power t5 t4 Partition 1 Partition 2 Partition 1 Partition 2 We tend to obtain a solution that power for each partition is similar to each other while the maximum power is minimized. Thus, the total power of our solution is also small. In contrast, total power minimization ignores balancing and peak power minimization. t6 t6 39

40. Voltage Island Shutdown • When all blocks in a voltage island are not in use, the entire island can be shutdown to reduce power. CiprianSeiculescu, SrinivasanMurali, Giovanni De Micheli, “NoC Topology Synthesis for Supporting Shutdown of Voltage Islands in SoCs,” DAC’09. AshokaVisweswaraSathanur, Luca Benini, Alberto Macii, EnricoMacii and Massimo Poncino, "Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction", ISLPED’08. David E. Lackey, Paul S. Zuchowski, Thomas R. Bednar, Douglas W. Stout, Scott W. Gould and John M. Cohn, "Managing power and performance for System-on-Chip designs using Voltage Islands", ICCAD’02. Qiang Ma and Evangeline F.Y. Young, Voltage Island-Driven Floorplanning, ICCAD’07. 40

41. Shutdown v.s. Peak Power Reduction • Previous works assume that the shutdown frequency for each voltage island is known. • They design application specific floorplan good for known shutdown frequency • Valid for some very specific applications • Not valid for general applications • Shutdown frequency depends on input data, which are quite difficult to predict. For example, whether the user will surf the internet more or watch DVD more is not known 41

42. Our Philosophy • Previous works start their floorplan optimization with a random floorplan and gradually tune it for power minimization under the assumed shutdown frequency • This work advocates that they should start with a generally good floorplan and then tune it for any given shutdown frequency • Generally good means a floorplan where the largest power among all voltage partitions is minimized • When you do not know shutdown frequency, it is reasonable to assume that voltage islands are shutdown with similar frequency • At least, for those blocks without definite answers on shutdown frequencies for general application • Applicability of Our Voltage Partitioning • Our formulation targets to be applied to those circuit blocks without definite answers on shutdown frequencies • As a byproduct, power consumptions over these voltage partitions are well balanced 42

43. Problem Formulation • Given a set of voltage levels, a set T of n functional units, the capacitance and minimum voltage of each functional unit, and a set of discrete voltage levels, to compute a voltage partitioning solution with m partitions such that the peak power over all partitions is minimized. 43

44. NP-Completeness Proof • Decision version of our problem when m=2: given an integer p, whether there is a voltage partitioning solution {T1,T2} satisfying max P(Ti) ≤ p • The known NP-hard bipartition problem: given an integer w, whether n integers {a1, a2, … an} can be partitioned into two groups {A1, A2} satisfying |∑A1-∑A2| ≤ w • Without loss of generality, assume that all integers are even numbers. 44

45. p Î v ( t ) ( , 1 ) i + p 1 max ( T ) p P £ i i Instance Construction set c(ti)=ai, M=∑ c(ti), and p=M/2+w/2 An instance for bi-partition |∑A1-∑A2|≤w An instance for voltage partitioning 45

46. p Î v ( t ) ( , 1 ) i + p 1 Reduction (only if direction - I) • Given a solution for the peak power driven voltage partitioning problem, 46

47. Reduction (only if direction - II)) 47

48. Reduction (if direction) • Given an instance of the bipartition problem, 48

49. NP-Completeness Theorem • Theorem 1: The voltage partitioning for peak power minimization problem is NP-complete. 49

50. Our Approximation Algorithm • A Fully Polynomial Time Approximation Scheme (FPTAS) • For any approximation ratio ɛ • Within (1+ɛ) optimal peak power for any ɛ>0 • Runs in time polynomial in n and 1/ɛ • Best solution for any NP-hard problem in theory