STATIC pre-CDR Peer Review 2011 May11

1. STATIC pre-CDR Peer Review 2011 May11 Instrument Lead: James McFadden Electrical: Ken Hatch, Rick Sterling, Dorothy Gordon, Chris Tiu, Peter Berg, Selda Heavner Mechanical: Greg Dalton, Greg Johnson, Paul Turin Testing: Onno Kortmann, Mario Markwordt

2. Overview Introduction McFadden Requirements Status at PDR Design Changes Front End Electronics Hatch Digital Electronics Sterling FPGA Gordon Carbon Foils Kortmann Mechanical Design Dalton Schedule/Wrap Up McFadden

3. Summary of Science Requirements STATIC Science Objectives and Requirements • Thermal Ionospheric Ions (0.1-10 eV) • - >1 eV due to RAM velocity (~4 km/s), peak flux at ~4-5 eV • - densities of 105/cm3 require both attenuators • - densities of 103-104/cm3 require single attenuator • - resolve 3D angle distribution requires ~10-20 deg sensor resolution • - resolve parallel temperature down to ~0.1 eV requires ~1 eV • Suprathermal Ion Tail – Conics (5-100 eV) • - >5 eV ions with escape velocity • - expected fluxes similar to Earth’s aurora • - as RAM ions drop below ~102/cm3, switch off attenuators • Pick-up Ions (100 – 20,000 eV) • - tenuous flux may require long integrations • - flux generally maximum perpendicular to solar wind V and B • - optimal measurements may require rotation of APP • - instrument should not saturate in magnetosheath

4. STATIC Characteristics • STATIC Geometric Factor • Nominal analyzer 0.016cm2-sr-eV/eV • With grid and TOF efficiencies : ~0.2 x 0.016 = 3x10-3 cm2-sr-eV/eV • With electrostatic attenuator only 3x10-4 cm2-sr-eV/eV • With mechanical attenuator only 3x10-5cm2-sr-eV/eV • With both attenuators 3x10-6cm2-sr-eV/eV • STATIC Dynamic Range • Energy flux range <104 to 108 eV/cm2-s-sr-eV (nominal-isotropic), • Energy flux extended to 1012 eV/cm2-s-sr-eV w/ attenuators, low energy beam • 360o x 90o FOV less s/c blockage (<25%) • 1 eV to 30 keV • 1 amu to 70 amu • STATIC Counting Rate and Background • Electronic dead time ~0.5 μs • Attenuators should be activated when rate exceeds 400 kHz • Coincidence rejection reduces background to negligible levels • STATIC Resolution • Analyzer intrinsic energy resolution, dE/E~15% • Angle resolution 22.5o x 6o • Mass resolution m/dm>4 • Fastest time resolution is 4 seconds, some products averaged for 2 minutes

5. STATIC Mounting on APP STATIC is mounted on the 2-axis APP boom to reduce s/c wake effects and to point the sensor FOV to include both the RAM direction (i) and nadir (roughly j).

6. STATIC Block Diagram Starting from the top: 1) Ions are energy selected by the analyzer 2) Ions post accelerated by 15 kV 3) Ions penetrate Start foil producing e- 4) Start electrons accelerated and deflected to the MCP producing signal in Start anodes 5) Ions traverse 2 cm and penetrate Stop foils producing e- 6) Stop e-, accelerated by ~10 kV, penetrate thick foil (-4-5 kV), strike MCP producing signal in Stop anodes 7) Protons penetrating Stop foil are captured by thick foil before reflecting 8) Heavy ions may reflect before thick foil, due to energy losses in foils, but have high efficiency for foil e- production 9) Separate delay line anodes for Start and Stop signal allows both position and time coincidence for rejection of noise. 10) Digital interface board decodes and stores event before transfer to PFDPU 11) 4 sec cycle time 64E x 16 Deflections

7. STATIC Design Features • Selectable noise threshold for setting valid events to be analyzed by TDC • Variation of event threshold can be used to measure MCP pulse height distribution and keep MCP voltage optimal • Large preamplifier dynamic range to accommodate variations in MCP PHDs • Large sweep HVPS dynamic range to accommodate thermal ionosphere and pickup ions – includes relay for in-flight measurement of Opamp offset drifts. • Noise rejection based on requiring TOF1=TOF2 and POS1 = POS2 • Test pulser with variable gain and start-stop delay time. • Backup mode to retain mass discrimination should one preamp fail. • Two attenuators that provide 3 separate geometric factors allowing gradual changes in sensitivity with region. • Attenuators are controlled by PFDPU and will be actuated based on count rate with an algorithm that incorporates hysteresis. Mechanical attenuators will only cycle once per perigee pass. • TOF detection efficiency can be easily determined in-flight based on ratios for Starts/(Starts+Stops) and Stops/(Starts+Stops). • Absolute detection efficiency can be determined to better than 20% accuracy from simulation of analyzer, grid transmission estimates, and TOF efficiency. • In-flight cross calibrations can be made with SWEA, SWIA and LPW(fp) in the magnetosheath, and with LPW(current sweeps) and NGIMS near perigee. • Instrument health is monitored by the PFDPU. • 6 levels of HV safing to prevent HV in inappropriate environments

8. STATUS at PDR • Subsystems with prototypes at PDR • 1) TOF analyzer with carbon foils • 2) Delay line Anode w/ MCP mounting • 3) Preamplifier Board • 4) Time-to-Digital Board (TDC) • 5) High Voltage Connector • 6) TOF HV supply (14kV) • 7) Sweep/Deflector HV supply (+/-4 kV) • 8) Digital Interface Board • Subsystems without prototypes at PDR (standard designs) • 1) Electrostatic analyzer with deflectors (spare ESA used for testing) • 2) Aperture opening mechanism with mechanical attenuator • 3) MCP HVPS and sensor LVPS • 4) GSE interface (Stereo GSE used for testing) • Primary concerns during EM development • 1) Front end noise/jitter characterization (required fast scopes for sub-ns testing) • 2) Reliable carbon foil mounting and verification (development of procedures) • 3) Large dynamic range for sweep HV (low noise and offset drift testing) • Mechanical mechanism for aperture opening and for mechanical attenuator • 5) Critical parts must pass stress/radiation testing

9. Overview of EM Development • Subsystem development since PDR • 1) All prototype boards required new layouts (part changes or obsolete layout software) • 2) EM Preamp-Anode testing showed larger dynamic range needed (2 preamp designs) • 3) EM TDC testing shows some cross-talk jitter between start/stop (layout mods needed) • 4) EM digital board modified for a FPGA daughter card and new test pulser (in Test) • 5) EM Acc/MCP HVPS (-15, -14, -6, -5, -3.7kV) modified to use VMI parts (being loaded) • 6) EM Sweep/Deflector HVPS (+/-4 kV) modified to reduce noise (in Test) • 7) EM LVPS designed and built (waiting for EE to begin testing) • Carbon foil mounting and testing procedures developed (vibration and acoustic tests) • 9) EM TOF analyzer fabricated (vibration and acoustic tests performed) • 10) EM electrostatic analyzer design completed (in fabrication) • 11) EM electronics box fabricated (board fit tests completed) • 12) EM external harness design completed (parts in fab) • GSE testing of digital board in process (test scripts being developed) • 14) Assembly procedures for TOF developed • 14) Clean room built for sensor assembly • 15) New Calibration Chamber in development (completion date July) • Primary EM testing milestones over next few months • 1) Life test for mechanical attenuator/opening mechanism • 2) Vacuum test of EM Acc/MCP HVPS with VMI parts • System level test with all subsystems operating in vacuum • Interface test to PFDPU

10. EM Anode Development Modifications from prototype layout to EM 1) Switched from pogo to Huber-Suhner MMBX and MMBC co-axial connectors 2) New layout in PADS

11. EM Anode Tests • Tests • Tested for relative signal degradation on Start and Stop transmission lines. • Tested for relative signal delay on the Start and Stop transmission lines. • Stop showed longer delays due to combination of line length and anode vias. • Total delay difference less than 2 ns • Anode test pulse inputs checked with Fast (sub-ns) test pulser. • Modifications to EM during testing to increase input test charge pulse • Test input capacitors increased from 1 pF to 5 pF • Test input drain resistors increased from 200 Ω to 10kΩ • Flight Anode modifications • 1) Single via for each stop anode (current design slows signal down) • 2) Make line traces on Start and Stop anodes identical in length • 3) Remove the heat sink traces on the anode pads

12. EM Preamp Development • Modifications from prototype to EM to provide more dynamic range • New layout in PADS with Huber-Suhner MMBX connectors • 1st stage of 3 transistor preamp modified to be more linear • 3) Two versions of preamp design being pursued for more dynamic range • a) Version 1 is nearly identical to prototype (except for 1st stage) ~25-30 dB range • b) Version 2 has a modified stage 2-3 for more linear gain ~35-40 dB range

13. Preamp Dynamic Range H+ O+ Pulse Height Dist. 0 1e7 4e7 Gain • Larger preamp dynamic range needed to prevent saturation and timing degradation • Different ion species produce different pulse height distributions • a) Protons typically produce a single electron from the carbon foils • b) Oxygen or other higher mass ions can produce 2-6 foil electrons • c) Therefore preamp dynamic range should allow factor of at least 4 in peaks in PHD • Preamp threshold should be at least a factor of 2 below proton peak PHD • Signal loss by delay lines introduces factor of 2 difference in gain into the preamp • Non-ideal MCP gain (due to non-optimal bias voltage and/or non-uniform gain with position) suggest at least another factor of 2 in dynamic range needed. • Therefore, to maintain margin on TOF timing accuracy, we’d like to have a factor of >32 in preamp dynamic range (>30 dB) where signals are not saturated above the noise threshold. A minimum dynamic range would be ~20, and would introduce some timing errors for the largest signals.

14. Preamp Dynamic Range Prototype preamp had inadequate dynamic range (~8) to maintain timing accuracy over the range of input pulse amplitudes. It also had an incorrect gain, and was non-linear at small signals due to minimal idle current. 1) Preamp-TDC noise threshold is ~30 mV (tests with digital board indicate ~15 mV) 2) Maximum preamp output pulse voltage w/o saturation is ~3 V Therefore a preamp linear dynamic range of ~100 is possible 3) To keep the preamp power low, the DC transistor CE current should be minimized. 4) However, event signal currents can be much larger than the DC current. 5) Since the transistor’s frequency dependent gain depends strongly on CE current, gain changes with input signal size will change the shape of the output pulse 7) CFD timing accuracy depends on maintaining constant shape for the preamp output A trade was needed between minimizing DC current (power) and preamp linearity Two preamp solutions are being evaluated. The first solution involves only changes to the first transistor stage – to make it more linear and shape the pulse. This provides a factor of ~20 in dynamic range. The second solution involves a more extensive preamp redesign and should provide an additional factor of 2 in dynamic range and less timing drift w/ amplitude.

15. EM Preamp Test Data 1

16. EM Preamp Test Data 1

17. Changes to Preamp • Change bias current in 1st stage to higher value to improve linearity. • Add input filter to obtain better input stage response. • Improve dynamic range of output stage.

18. Original preamp design Limited dynamic range Huge current swing in Q1

19. New Input Stage Design (for better linearity)

20. Alternate preamp design (for improved dynamic range) Input slowing network Wide dynamic range gain stage Need temperature compensation, possibly series diodes for V_Tcomp (feeds all 4 stages)

21. EM TDC Development • TDC modifications from prototype to EM • New Layout in PADS • Inter-board coaxial connections with Huber-Suhner MMBX connectors • New 21 pin TDC to digital board connectors selected • Part changes to accommodate NASA specs.

22. EM TDC-CFD Modified Schematic • Testing uncovered …. • ADC inputs and reset lines floating when not hooked up to digital board • Timing comparator in unknown state when latched (made testing difficult) • 3) Race condition was marginal for threshold enable of timing comparator latch • Start/Stop timing jitter (~1ns) when Stop signal was ~15-17 ns after Start. • Inconsistent TDC timing capacitor discharge circuit design • Fixes • Pull down resistors will be added to flight TDC layout • Threshold voltage introduced into timing comparators to assure latched signal is low • Timing comparator’s 2 ns delay line chips replaced with 3 ns delay line chips • Will move threshold flip-flop closer to threshold comparator, add power line filtering, change the ground plane • Determined the proper discharge RC circuit for holding timing capacitor at ground. • Other Testing • Linearity of TOF timing • Preamp-TDC timing drift with input signal amplitude (1-1.5 ns over 25-30 dB) • Delay requirements between pulse and ADC latch as a function of TOF time.

23. TIMED schematic

24. TDC original design

25. EM TDC Test Data 1

26. EM TDC Test Data 15 ns delay

27. EM TDC Test Data 17 ns delay

28. EM TDC Test Data 18 ns delay

29. EM TDC Test Data 20 ns delay

30. EM TDC Test Data 40 ns delay

31. Changes to TDC Board • Add pull-ups and pull-downs for easier testing (Establishes high or low for open pin). • Copy best reset circuit to all resets. (resets charge on integrating capacitors.) • Change CFD delay chips to 3 ns to provide margin on race condition for threshold enable of timing comparator latch • Make changes to ‘stop’ timing discriminators to isolate noise. • Redo layout to isolate ground and power associated with stop discriminator.

32. Added resistors R636 through R644 (places board in known state when pin is disconnected)

33. Use this circuit for all resets

34. TIMED schematic U203-1 U212 U203-2 Replace 2 ns delay chips with 3 ns

35. TDC EM Layout (U212 traces cross start section to get to U203)

36. Changes to “stop” timing discriminator Added part Moved connection 3 ns delay chips

37. New Layout (U203 and U212 are close) U203 U212

38. New Layout Isolated ground

39. EM Digital Board Development • Modifications from prototype to EM • 1) Daughter Card Added for FPGA • 2) A few part changes for reduced power consumption or part consistency. • 3) Flight mating connectors: MDM21 mating to TDC, HDLP connectors for daughter card., Huber+Suhner test pulse connectors.

40. EM Digital Board Tests Completed

41. Static Digital Board Testing Anode/PreAmp-TDC-Digital--MISG -------GSEOS End to end testing on the bench.

42. Test Setup • End to End Testing with Controllable Test Pulses • Pulses generated on command at FPGA in Digital Board • Pulses can be controlled in frequency, amplitude and delay • Pulses Sensed at Anode and results sent through entire chain

43. Test Pulse Design Modifications Modified circuit design to minimize ringing, minimize over/undershoot, yet have fast (1 ns) fall time. Trimming resistors, added diode.

44. Issue: Missing Signal Discovered missing signal. Pulse clearly seen at input to Digital Board and via on backside of FPGA. Not being received at FPGA. Jumpered to another pin to move forward. Will replace FPGA and retest. Flight boards use CCGA.

45. Sample Test Data 1 Sample screen shot with counts which are checked against Test Pulse settings. Example: Start-Stop Time.

46. Sample Test Data: Rates Display of pulse count rates. Easily compared with Test Pulse frequency.

47. EM Digital Board Testing TBD EM Digital Board Tests To Be Done: * Voltage Margin Test. Vary voltages +/- 10% at ambient, hot (+65C) and cold (-35C). * Parts Stress Analysis. Use GSFC spreadsheet/analysis to determine stress on each individual component in design.

48. Clean Room for sensor assembly

49. Sink for Carbon Foil Mounting

50. New Cal Chamber being constructed