IBM 0.13um Update

1. IBM 0.13um Update 9/8/08

2. 0.13um CML Driver with Pre-Emphasis • Added second pre-emphasis tap • Added control for levels of each tap No emphasis 1st tap emphasis 2nd tap emphasis • Beginning work on equalizer design…

3. 0.13um Opto-Chip Prototype • Received Opto-Chip prototype in July from CERN / MOSIS • Found all sections (VDC, PLL, DORIC) to be functional (more details to come) • Have so far performed measurements on only macro-packaged (PLCC) die in preparation for irradiation • Plan to perform measurements in packages / setups with smaller parasitics in the coming months

4. 0.13um Opto-Chip Prototype: VDC • Submitted 2 separate VDC types: • “Fast” – 3.2 GB/s • Optimized for speed, lower drive currents • “Slow” – 640 MB/s • Optimized for B-Layer replacement speeds (640MB/s), higher drive currents

5. 0.13um Opto-Chip Prototype: VDC • Both varieties operate well even in non-optimal package / setup • Driving a packaged VCSEL (Optowell), light received by a 4Gb/s commercial SFP transceiver • “Slow” VDC operates with BER less than 10-13 at 1 GB/s • “Fast” VDC operates with BER less than 10-13 at 3.2 GB/s • This work also validates the operation of our LVDS receiver at high rates 0.13um chip in PLCC package VCSEL in can

6. 0.13um “Slow” VDC @ 640MB/sDriving 2.5GB/s Optowell VCSEL

7. 0.13um “Slow” VDC @ 1 GB/sDriving 2.5GB/s Optowell VCSEL

8. 0.13um “Fast” VDC @ 1 GB/sDriving 2.5GB/s Optowell VCSEL

9. 0.13um “Fast” VDC @ 3.2 GB/sDriving 2.5GB/s Optowell VCSEL

10. 0.13um Opto-Chip Prototype: DORIC • Submitted one variety capable of decoding BPM encoded data at 40MB/s, 160MB/s, and 320MB/s • Received chips decode BPM data and clock at 40MB/s, 80MB/s, and 160MB/s…Problem seems to be simple mistake but have yet to determine the cause…

11. 0.13um Opto-Chip Prototype: DORIC • LVDS driver works well: • rise / fall time = 125 ps • Top = 1.1 V, Base = 0.625 V, Amplitude = 475 mV • Recovered Clock Jitter (Std. Dev. Pos. Wid.) • 40 MHZ < 250ps • 80 MHz < 100ps • 160 MHz < 50ps • Supply Current @ 1.5 V = 30mA • BER threshold (Pk-Pk) • 40 Mb/s ≈ 60uA • 80 Mb/s ≈ 100uA • 160 Mb/s ≈ 150uA

12. 0.13um Opto-Chip Prototype: Clock Multiplier / PLL • Submitted two PLLs, one a 4X multiplier and the other a 16X multiplier • Needed to multiply recovered 160MHz / 40MHz clock up to 640MHz for serialization • Both PLLs work as expected • Jitter for both 4X and 16X < 8ps, only 0.5% • Current consumption @ 1.5 V = 35 mA

13. 0.13um Opto-Chip Irradiation

14. 0.13um Opto-Chip Irradiation • Irradiated 16 Opto-Chip prototype die to a dose of (hopefully) 3x1016 protons / cm2 ~ 85 Mrad • Tested: • 8 VDCs • 4 “Slow” • 4 “Fast” • 4 Clock Multipliers • 4 Purely Electrical DORICs • 4 DORIC + 4 Si PIN (Taiwan) • Due to limitations in the cabling available could only operate DORIC / VDC at 40Mb/s • Designed special card to allow testing of PLL at 640MHz

15. 0.13um Opto-Chip Irradiation: VDC • VDCs driving a 25 ohm resistor with constant iset and 40MHz input signal for entire irradiation period • During VDC irradiation noticed significant drop in supply and output current • Duty Cycle remained within spec. • Cause still unknown but by increasing iset, signal / current consumption gets larger • Possible causes: • Chip not rad-hard? • Non-rad hard resistors used on test card? • Will compare before / after rise / fall when chips are cool enough to return to Ohio (cable lengths too long for reasonable measurement ~ 20 meters)

16. VDC 2.5 V Current Consumption(VCSEL DRIVER CURRENT)

17. VDC 1.5 V Current Consumption(LVDS RECEIVER CURRENT)

18. VDC Output Duty Cycle

19. “Fast” VDC Bright / Dim Currents

20. “Slow” VDC Bright / Dim Currents

21. 0.13um Opto-Chip Irradiation: Purely Electrical DORIC • Tested 4 DORIC chips with purely electrical input signal • sent variable size signal over 20m of coax to DORIC input • Operated with 40 MB/s BPM encoded input signal (long cable prohibited operation at higher speeds) • Performed lower BER threshold measurements (1 error per second) saw no degradation • Observed SEU, dependent on input signal size • Plots not ready yet… • Proves that LVDS driver in DORIC can drive ~20m of twisted pair at 40MB/s

22. Purely Electrical DORIC Total 1.5 V Current Consumption

23. Purely Electrical DORIC Lower BER Thresholds

24. Purely Electrical DORIC Errors per incident Proton – all data

25. Purely Electrical DORIC Errors per incident Proton – after 80 Mrad

26. 0.13um Opto-Chip Irradiation: Si PIN + DORIC SEU • Tested 4 DORIC chips connected to 4 separate Si PINs from Taiwan to look at SEU • sent light to PIN over 35m fiber • Operated with 40 MB/s BPM encoded input signal • Performed lower BER threshold measurements (1 error per second) saw no degradation • Observed SEU, dependent on input signal size • Much worse than DORIC alone as expected • Plots not ready yet

27. SEU DORIC Total 1.5 V Current Consumption

28. SEU DORIC Lower BER Thresholds

29. SEU DORIC Errors per incident Proton – all data

30. 0.13um Opto-Chip Irradiation: Clock Multiplier / PLL • Tested 4 PLL chips • used VDC / VCSEL in beam zone to send 640MHz to control room for viewing • Used fast scope (1GHz input bandwidth sampling at 10Gb/s) to attempt to capture SEU • Found 2 of the 4 chips lost lock while in beam and required power cycling to resume operation at 640MHZ • Could not capture the actual loss of lock event • In process of running a long term test on the bench at OSU to see if the chips loose lock with no beam, nothing seen yet. • No change in current consumption over 85Mrad

31. PLL Total 1.5 V Current Consumption

32. PLL upsets • Trigger (Channel 3) on DORIC error to know when spill has arrived (spill is 400ms long so we have a fairly wide margin of error) • Can sometimes see that PLL is perturbed! • Spills do not always cause perturbation • Much data taken so effects will be quantified and reported in more detail later

33. Chip 1 Normal Operation Outside of Spill Freq. = 641.157 MHz Std. Dev. = 28.258 MHz

34. Chip 1 Normal Operation During Spill Freq. = 640.03 MHz Std. Dev. = 4.439 MHz

35. Chip 1: Spill disturbs PLL Freq. = 727.115MHz Std. Dev. = 289.927 MHz

36. Chip 1: Spill disturbs PLL

37. Chip 1: Multiple errors (“big” spill), PLL untouched

38. Chip 1: Lock Lost!

39. Conclusion • First 0.13um submission mostly successful • VDC Channels Operate with BER < 10-13 at specified signaling rates even when used in non-optimal setup • Proves that LVDS receiver works at up to 3.2GB/s! • Clock Multiplier / PLL operates with low jitter • DORIC works at rates foreseen in B-Layer upgrade • Radiation / SEU tolerance results mixed • VDC output current decreases with dosage • Could be due to problem in Iset / Tunepad circuit or could be non rad-hard resistor on test card? • Duty cycle remains nearly constant up to 80MRads • LVDS receiver current remains unchanged • Clock multiplier / PLL can loose lock due to spills • Currently performing long term study to see if multiplier looses lock on bench • Need to attempt to recreate in simulation • DORIC current consumption / thresholds flat up to 80Mrads • SEU seen in purely electrical DORIC test (no PIN diode used) • Need to find cause and attempt to fix