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Status report

Status report. 2011/2/4 Atsushi Nukariya. Progress. ・ Progresses are as follows. 1. I created wave form which Fusayasu-san showed. → Rearrange design. → Change clock frequency. → Add another clock. 2. Chip test. 3. I created function which resets FPGA and Chip.

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Status report

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  1. Status report 2011/2/4 Atsushi Nukariya

  2. Progress ・ Progresses are as follows. 1. I created wave form which Fusayasu-san showed. → Rearrange design. → Change clock frequency. → Add another clock. 2. Chip test. 3. I created function which resets FPGA and Chip. 4. I’m revising the software which reads data from SiTCP.

  3. Wave form (1) ・ Requested wave form is as follows. → This is wave form about LSI, not internal on FPGA. → RCLK is stopped 1 RCLK when “EMPTY (0x200000)” is sent. → To stop RCLK, it needs clock whose frequency is two times as much as RCLK’s frequency. → Current design can’t implement this behavior. → Rearrange design. Input Data RCLK RADDRESS FIFOSEL

  4. Signal Processor GEMFE2 RCLK Controller SiTCP Clock Generator MCLK(10MHz) 10 MHz Crystal Unit RCLK(20MHz) HCLK(100MHz) Wave form (2) ・ Current design is as follows. Enable signal

  5. Enable signal Signal Processor RCLK Controller GEMFE2 SiTCP Clock Generator Clock Generator MCLK(10MHz) Crystal Unit 10 MHz RCLK(20MHz) RCLKx2(40MHz) HCLK(100MHz) Wave form (3) ・ New design is as follows. → The Xilinx tools can’t make this, because number of DCM is limited to 1.

  6. Wave form (4) ・ Revised design is as follows. → The Xilinx tools implements this design with no problem. Enable signal Signal Processor RCLK Controller GEMFE2 SiTCP MCLK Generator Clock Generator 10 MHz MCLK(5MHz) Crystal Unit RCLK(10MHz) RCLKx2(20MHz) HCLK(50MHz)

  7. Wave form (5) ・ Created data is as follows. ( Simulation. ) RCLK_C RCLKx2 MCLK Data Input HCLK RCLK Counter FIFOSEL DBuffer Output FIFOx3 Output SiTCP Input

  8. Wave form (6) ・ Created data is as follows. ( Simulation. ) → This wave form is corresponds to wave form which Fusayasu-san showed.

  9. Chip Test (1) ・ We searched value which chip works correctly. ・ This is wave form from Logic-Analyzer when RCLK frequency is 2 MHz. ( In first design, RCLK frequency is 10 MHz. )

  10. Chip Test (2) ・ When RCLK frequency is 4 MHz, there are crosstalk and noise.

  11. Chip Test (3) ・ When RCLK frequency is 10 MHz, most of output data are crosstalk and noise. → If chip works correctly, there is signal at RADDRESS 0 and 1 only. → More detail research is in progress.

  12. Reset ・ I created function which resets FPGA and chip. → When state isn’t STATE_TRANSFER, FPGA and chip will be reset at all time. → After state becomes STATE_TRANSFER, state becomes STATE_WAIT at 128 * 16 RCLK. ( Sequence diagram is as follows. )

  13. FPGA GEMFE2 Input D-Buffer FIFO Data Generator SiTCP Output Result (1) ・ I tested FPGA. → First part of output data and setup are as follows. (1) 0x061222 (2) 0x08CB33 (3) 0x0B91AA (4) 0x0DD155 (5) 0x200000 (6) 0x048923 (7) 0x008145 (8) 0x0C1178 (9) 0x0F8BB7 (10) 0x200000

  14. Result (2) ・ Result is as follows. ( Software is SiTCP Utility. )

  15. FPGA GEMFE2 Input D-Buffer FIFO Data Generator SiTCP Output Result (3) ・ I tested FPGA. → Setup is as follows.

  16. 10.4us 12.8us Result (4) ・ Input wave form is as follows. → This value is determined in consideration of DAC’s threshold. Offset : 1.25V Amp : 250 mV

  17. Result (5) ・ Result is as follows. → But this data doesn’t make a sense, because software has a bug. → I’m revising the software.

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