'Seu' presentation slideshows

Sandro Bonacini

474 views • 35 slides

Sandro Bonacini

502 views • 35 slides

Status of measurements of FE-I4 SEU and PRD

316 views • 23 slides

351 views • 20 slides

A Novel, Highly SEU Tolerant Digital Circuit Design Approach

A Novel, Highly SEU Tolerant Digital Circuit Design Approach. By: Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX. Outline. Background and Motivation Previous Work Our Approach Experimental Results Conclusions.

320 views • 19 slides

A Novel, Highly SEU Tolerant Digital Circuit Design Approach

A Novel, Highly SEU Tolerant Digital Circuit Design Approach. By: Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX. Outline. Background and Motivation Previous Work Our Approach Experimental Results Conclusions.

198 views • 19 slides

SEU WK summary

233 views • 15 slides

TMB Mezzanine SEU Testing Preliminary Results

268 views • 12 slides

114 views • 11 slides

August 2011 GR SEU measurements of FE-I4

August 2011 GR SEU measurements of FE-I4. A.Rozanov , 10.08.2011. August 2011 SEU measurements. Same two FE-I4-A Chip27and Chip28 installed in IRRAD3 proton beam PS CERN Beam available untill 15.09.2011

199 views • 9 slides

Irradiation Test of the Virtex-5 Muon Port Card Mezzanine

Irradiation Test of the Virtex-5 Muon Port Card Mezzanine. Devices Under Test. XC5VLX110 FPGA. XCF128X PROM. Firmware for the Irradiation Test. ? Two pipeline chains, 16-bit wide and 10,000 (10) steps deep ? Pseudo-Random Bit Stream Generators as data sources

200 views • 6 slides

Abstract

An SEU-Robust Configurable Logic Block for the Implementation of a Radiation-Tolerant FPGA S. Bonacini 1,2 , K. Kloukinas 1 , F. Faccio 1 and A. Marchioro 1 1 CERN, European Organization for Nuclear Research, Geneva, Switzerland 2 Institute National Polytechnique de Grenoble, France.

121 views • 2 slides