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EE210 Digital Electronics Class Lecture 10 April 08, 2009

EE210 Digital Electronics Class Lecture 10 April 08, 2009. Home Work No. 5 (Due April 15, 2009 ) Problems at the End Of Chapter 10 . Problem D10.25 Problem D10.26 Problem D10.46 Problem D10.47. In This Class. We Will Continue to Discuss : Complete CMOS Gates

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Lecture #26 Gate delays, MOS logic

Lecture #26 Gate delays, MOS logic. Today: Gate delays Another look at CMOS logic transistors. V DD = 3V. V IN =3V. +. V OUT. R N. -. t D. V SS = 0V. V OUT. Output when:. V DD = 3V. V IN jumps from 3V to 0V. -. R P. 3. V IN =0V. +. V IN jumps from 0V to 3V. V OUT.

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Chapter 4

Chapter 4. Logic Families. Chapter Objectives. Understand the basics of digital Integrated Circuits (IC) Understand the different types of transistor logic Understand the concept of Metal-oxide Semiconductor (MOS) digital ICs Understand the different types of BiCMOS logic circuits.

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Mos logic - PowerPoint PPT Presentation

EE210 Digital Electronics Class Lecture 10 April 08, 2009

Lecture #26 Gate delays, MOS logic

Chapter 4